Monday, February 18, 2008


Antenna Effect: During the processing of VLSI chips,the wafers can
collect charges.If a long metal line is getting connected to a gate
(which typically will be) ,and if this strip of metal collects
enough charges to breakdown the gate,the gate gets damaged
permanently. TO avoid this people use various techniques like going
to one metal above and coming back if they think that the metal strip
is very long.Other technique is to have a diode connected to the
metal line in a proper direction to discharge these extra charges.

Electromigration: As the name suggests,when very large currents flow
in a metal and if the metal is not able to carry that much current,
it(the metal strip) may get knocked out creating a open here,and
short somewhere else(plausible).Basically the metal width and
thickness should be sufficient to carry that much current.This is a
reliability issue.It can happen at any "micron" technology,not only

Cross-talk: This term is interchangeably used with coupling
capacitance. It is self-explanatory.

The reason for antenna effect is still debated.Whatever the reson is
like the metal line connected to a gate getting charged or
someother,if the metal line length to gate area is more than some
critical value,it is seen that gate gets damaged.So people tend to
limit the length of the metal line.

Are you considering the issue of cross-talk. Cross-talk is related to
line length and proximity of two lines. Thus, long adjacent lines can
couple better than short lines. Is this what you consider? Or, are
you purposely limiting the length of the line because of some other
manufacturing issue. Why impose a rule unless you understand the

Crosstalk is dynamic problem,ie when the device is in operation,it is
a speed issue,not a reliability issue.But,the thing being talked
about here is a reliability issue and it is related to the process.
The above section talks about the charges that would build up on the
metal interconnects during high energy plasma processes such as dry
etching in fabrication. These charges may eventually end up at and
cause damage to the thin gate oxide of the transistors. The charge
build up is understood to be due to plasma non-uniformity in the
reactors. The effect can be partly be prevented by maintaining
uniform plasma in the reactor as well as by providing on-chip
protection elements such as clamp diodes across thin gate oxides.
Design rules that take into account the antenna ratios i.e., for a
given gate oxide area, the maximum interconnect length and area that
can be supported before a protection diode is needed are usually

Antenna efects are are long floating interconnects that acts as
temporary capacitors during the metalisation process.Because a
conducting path to ground does not exist at the time of metalisation,
a random discharge from the floating nodes can cause permanent gate
oxide damage. Since it is a mater of capacitance, length and other
dimensions of the interconnect also plays a role. Solution: Inserting
buffers or diodes near the input pins to provide conducting path to
ground eleminates this problem And there is a way to minimize the no.
of charges collected by floating node by inserting jumpers.

Thursday, January 31, 2008

Using model-based design in signal integrity engineering

Using model-based design in signal integrity engineering

RF techniques, originally developed for wireless communication projects, are being repurposed to solve the increasingly complex problem of preserving signal integrity in high-speed data transmission between chips joined by backplanes and printed circuit boards. These pin-to-pin connections are becoming mini-communication systems in their own right. In parallel, Model-Based Design is being adopted for these projects to significantly speed the design process, through a graphical environment with prebuilt, optimized algorithms and blocks. This article addresses the convergence of these two trends.

Planning a typical application
We'll use Model-Based Design and RF techniques to create an impairment model of the backplane that is used as a test environment in both the modeling and design phases for the development of mitigating algorithms.

The first step is to use a vector network analyzer (VNA) to measure the frequency-domain response of the backplane and record it in an S4P (four-port) Touchstone file. Modified rational functions are then used to fit the frequency domain data to a time-domain behavioral transfer function. The resulting transfer function is used as a test environment in the development of mitigating algorithms in a Simulink® model. A Verilog-A version of the transfer function is generated for verification of the circuit design. The circuit design can be based on the model and completed using electronic design automation (EDA) tools.

Signal integrity challenges
The increasing speeds used in telecommunication and data communication infrastructures have made it more difficult than ever to achieve data transmission at sufficiently low bit error rates (BERs). A signal sent from a gigabit per second transmitter on the I/O pin of one chip travels first along a trace on a plug-in card, then across a backplane to another plug-in card that contains the receiving chip. The signal often becomes degraded by intersymbol interference (ISI), frequency-selective attenuation, and crosstalk. The ISI impairment is caused by reflections, typically caused in turn by impedance mismatch at various interconnection discontinuities. These impairments become more severe as the data rate increases. By contrast, when data rates are below 1 Gb/s, we can rely on a fairly flat backplane frequency response. Also, the echoes of previous pulses decay before the next one comes along, so ISI is less of an issue.

Today, data rates are usually well above 1 Gb/s, so the echo decay time is longer than the pulse spacing, and the received pulse is mixed up with echoes of the previous pulse. The job of signal integrity engineering is to mitigate this and other impairments. Design of adequate mitigating algorithms, such as a pre-emphasis filter for the transmitter and a decision feedback equalizer (DFE) for the receiver, requires an accurate model of the impairment.

The fact that the backplanes and the chips with the I/O transceivers are produced by different companies increases the complexity of the design process. In order to facilitate a dialog between these two groups, equipment manufacturers develop behavioral models of the backplane. Semiconductor companies use these models as a test environment for transceiver design. Chip companies furnish behavioral models of the I/O design so that backplane makers can check the range of backplane designs in which the transceiver can operate successfully. The design process naturally involves a fair amount of iteration because when the equipment manufacturer changes a design it may change the test environment for the chip maker and vice versa. The companies involved typically go back and forth modifying their designs and models until the complete system meets performance specifications.

Applying the modified rational function method
We can simplify the design process for the data transmission application using Model-Based Design. The transmission line will be modeled as a modified rational function using MATLAB and RF Toolbox . A modified rational function is a transfer function in the form of a particular type of Laplace transform. The general Laplace transform is the integral over time of a function of time f(t) with a complex sine wave e-st

In the modified rational function, f(s) consists of residues cjand poles ajwhich are complex conjugate pairs. Correspondingly in the time domain, f(t) consists of a direct feed term dδ(t-td) plus a set of exponentially decaying sine waves, which begin after the principle delay td

The modified rational function has the following advantages:

  • We can achieve the same level of accuracy as the IFFT method, with a model that is one or two orders of magnitude simpler.
  • Model order reduction can be used to trade off complexity and accuracy through the use of fitting parameters.
  • Typical VNA data has a low frequency cutoff at around 20 to 50 MHz, so an extrapolation to DC is needed. With IFFT models, there is nothing to prevent the extrapolated phase from being nonzero, which corresponds to a nonphysical delay.
  • This can be avoided by writing a constraint algorithm, but this takes time. In contrast, rational models represent a physical transmission line. So the phase on extrapolation to DC is inherently zero, avoiding the need for constraint algorithms.
  • The physical correspondence between the model and transmission line also provides greater insight when building mitigating algorithms. For example, seeing what poles exist on the transmission line is very helpful when building the DFE.

Fitting a rational function to VNA data
The first step is creating a model of the impairment using S4P data from the VNA. In this example, the S4P data includes about 1,500 frequencies from 50 MHz to 50 GHz. After reading the file into MATLAB via the RF Toolbox read function, we use the s2sdd function to extract the equivalent differential two-port behavior of this four-port network. The next step is to compute the transfer function and rational model. The frequency domain transfer function of the two-port parameters is calculated with the "s2tf" function. Then the "rationalfit" function is used to compute the time-domain modified rational function. The end result is that about 24,000 data points are condensed into a simple 48-pole rational function fit.

We can check the rational function and visualize it in MATLAB and RF Toolbox before the next step, which is to run a script that reformats the backplane model for use in Simulink.

1. Frequency response (above left) of a rational function model created from measured S-parameters. The model was used to create the eye diagram (above right) for analyzing intersymbol interference.

Modeling the backplane in Simulink
The reformatting script works by setting the coefficients of several existing Simulink blocks, joining them into a simple structure, and collecting the result in a subsystem. The poles and residues of the rational function model are converted into numerator and denominator form for use in the Laplace Transform transfer function blocks. Each transfer function block represents either one real pole and residue or a pair of complex conjugate poles and residues. Either way, each transfer function block always has real coefficients.

In this example, the rational function model contains two real poles and residues and 10 pairs of complex poles and residues, so the model contains 12 transfer function blocks. The principle delay is modeled with a Transport Delay block. Then the subsystem is exercised by connecting a simple test harness consisting of a random message source connected to input. Scopes and a BER meter are used to quantify the impairment. Once the subsystem is performing as expected, the next stage, not covered in detail here, is to develop models of the mitigating algorithms, such as pre-emphasis filters and DFEs.

2. The rational function model can be used in a Model-Based Design workflow, where algorithms that mitigate the impairment (such as preemphasis and equalization) are developed.

Modeling the Backplane in EDA tools
We can use popular EDA tools to create the circuit-level design based on the algorithms we modeled. To verify the design we'd like to reuse the impairment model in the EDA environment. We can do this by exporting the modified rational function once more, this time as a behavioral Verilog-A module, a preferred form for EDA tools.

The module includes the Verilog-A "laplace_nd()" function with the appropriate numerator/denominator coefficients. The principle delay is created using the Verilog-A "absdelay()" function. We can then run this Verilog-A module inside an EDA tool to verify the design of the circuitry that implements the mitigating algorithms.

3. The rational function model can be exported in Verilog-A behavioral format. This module is then imported into a mixed-signal circuit simulator, and is used in the design phase of Model-Based Design.

Design success
This example shows how system architects are using RF techniques and Model-Based Design to rapidly develop signal integrity systems and algorithms. Model-Based Design involves the creation of executable models in a block diagram design environment using blocks that represent algorithms or subsystems. A key to the success of Model-Based Design is the existence of libraries of prebuilt standard data transmission algorithms or blocks, such as digital filters, transforms, and spectral analysis tools. Libraries of visual blocks enable BER plots, constellation diagrams, and eye diagrams to be quickly and easily added to models.

These libraries enable systems to be built extremely quickly by dragging and dropping the algorithms or blocks from a library into the model and then joining the blocks. This flexibility also enables models to be changed very easily and quickly. The result is that engineers can focus their efforts on what's important, namely the algorithms and systems being tested.

Model-Based Design offers several major advantages for signal integrity engineering. The biggest is that models can be changed much more easily and rapidly than C code. The behavior of blocks can be changed quickly by altering their parameters. Structural changes can be made promptly by adding or removing blocks from a model by dragging and dropping " without the need to recompile the model. The results of changes can be examined using the visual blocks, for example, to show the BER after code has been added to a model. This allows different designs and algorithms to be evaluated extremely quickly. C-coded models cannot offer this level of flexibility. This makes Model-Based Design especially appropriate to signal integrity engineering.

About the Author
Colin Warwick is an RF Product Manager at The MathWorks. He is focused on the verification of RF, analog, and mixed-signal subsystems in the context of Model-Based Design for signal processing and communications applications. Colin can be reached at

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Signal integrity approaches meet the multi-Gbps design challenge

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Signal integrity approaches meet the multi-Gbps design challenge

start:Signal integrity approaches meet the multi-Gbps design challenge

High-speed data paths now lie on the critical path of product development; you can combine multiple approaches, including S-parameters, for effective signal-integrity analysis

The wireless explosion has spawned a frontier with countless market opportunities for communications companies. The increasing complexity of today's electronics products, however, has created a myriad of issues for designing and bringing to market these technology-rich applications. Electronic design automation (EDA) software is an important tool in the product generation process, and a key concern inherent in the design of next-generation, high-performance communications products is complex cross-domain signal integrity (SI) issues.

Signal integrity (SI) analysis has traditionally been used as a verification step prior to releasing a design for manufacturing. This methodology served the high-speed design community well as clock frequencies and data rates pushed through 100 MHz and approached 1 GHz. But with today's communications designs with data rates of 3 to 5 gigabits/sec (Gbps) and beyond, the fundamental assumptions that used to permit "fixing up" the timing at the end of the design cycle are no longer viable. High-speed data paths now lie on the critical path of product development and a new, more proactive approach to SI is needed.

Multi-Gbps design challenges

The design of high-frequency (above 1 GHz) interconnects can be an issue across all parts of the design, from on the chip itself, moving off the chip and through the packaging, and onto the board, or all of these at the same time. Communications companies who are developing products with increasing frequencies and edge rates, and using traditional printed circuit board (PCB) signal-integrity solutions, are finding that their designs look good in simulation (Figure 1a), but when they build and measure their prototypes they get very different and disappointing results (Figure 1b).

(Click on image to enlarge.)

Figure 1 (a) and (b). Simulated design results (upper image) vs. measured prototype results (lower image).

(Click on image to enlarge.)

Consequently, they find themselves spending excessive time and money on redesigns, re-spins, and experimenting on the test bench, adding cost to their final products not only with additional "fix-it" components (capacitors, inductors, etc.) but ultimately in lost time-to-market opportunities.

Why such large discrepancies between simulated and measured results? At frequencies up to several hundreds of MHz, interconnects can be modeled as lumped, passive-element RLGC or RLCK models. This modeling technique has been effective since the days when SI issues first surfaced starting with 33 MHz PC designs. A single lumped-element equivalent circuit model for interconnects was sufficient to capture high-frequency effects, and allow SI analysis to confirm that timing constraints and signal quality requirements were met.

But at GHz frequencies, with clock edges measured in picoseconds, the old lumped element approximations become grossly inadequate. Interconnects must now be modeled as coupled transmission lines with propagation and loss characteristics having strong frequency dependence due to dispersion, skin effect, and dielectric loss. The result is that the commonly-used RLCK modeling and simulation technology can no longer provide accurate or dependable results. High-frequency models and simulation technology must be incorporated to design, simulate, and validate a manufactured product that will actually work as designed.

Figure 2 displays a spectral analysis of a 1 GHz pseudorandom binary sequence (PRBS) waveform with 100 ps rise/fall edges.

Figure 2. Spectral analysis of a 1-GHz PRBS waveform
(Click on image to enlarge.)

The RLCG models provide enough accuracy up to about 1 GHz, but as this spectrum plot shows, depending upon the system signal-to-noise ratio (SNR), there is significant frequency content from a 1 GHz data rate out to 20 GHz and beyond.

Besides the speed of the signals and edge rates, designing across different manufacturing domains is also a critical issue. In order to optimize system-in-package (SiP) or module designs, it is important to be able to co-design individual die across packaging and sometimes with the PCB. In order to increase confidence in the design, the effects of all components in the signal path should be considered concurrently. A good design system must have the ability to simulate the entire path, including the IC or at least the IC I/O buffers, at the transistor level for the most accurate and dependable results. But most flows today are based on tools that do not permit this kind of seamless interaction between chip and board, and the electrical and physical domains.

Efficient design requires modern data modeling

Traditional EDA tools architectures were developed in the late 1980's and early 90's. The state of the art then was to have a unique database for each step of the design flow and to then integrate databases with layers and layers of software called "frameworks" (Figure 3).

Figure 3. Traditional EDA tools with separate data files for each step vs. modern solutions with a single unified data model.
(Click on image to enlarge.)

The result was that each step of the design process—or "view" of the design—had its own database and its own use-model. This delivers a very serial flow, with any given engineer only able to master one or two steps or tools in the flow. The result is that the design is spread out over many different tools, and it is difficult or impossible to ensure that all the data is synchronized. Synchronization of the design can take hours, days, or weeks, if it happens at all.

More modern solutions have been introduced in the past ten years which offer a completely different approach through a single, unified data model. These include several new technologies that have recently matured: C++ and object-oriented design, and component object modeling and databases. The newer solutions, such as AWR's SI® design suite, which was used in the design methodology for this paper, enable all of the tools or views needed to design GHz electronics to be inherently synchronized by using the same database.

This results in much shorter design cycles, because there is no extra effort needed to synchronize the design. Such an arrangement of single database with multiple tools/views is sometimes referred to as a unifying or unified data model (UDM). With a UDM, there is also no penalty in terms of time or data lost (from incomplete translations) in switching between different steps in the flow.

For the SI analysis flow in flux at multi-Gbps rates, the UDM is a potential solution. Rather than having to wait until very late in the flow to have access to completed layouts for post-layout SI analysis, the UDM provides early incremental access of electromagnetic (EM) simulation results to the SI engineer prior to, or as part of, formal PCB layout. In this way, interconnects for critical serial links can not only be designed before the integrating PCB layout step, they can also be analyzed post-layout, thereby providing a greater degree of certainty that the interconnects will perform adequately at frequency.

Furthermore, the UDM has the ability to concurrently manage multiple stack-ups, or technology files, representing the ICs, their packages, the PCB, and all associated die-to-board electrical models. This gives the SI designer much more flexibility for verification. No longer is it necessary to extract macro-models of IC-level components for simulation with package- and PCB-level models. The SI engineer can now co-design module-level interconnects with driver and receiver circuitry at the transistor level, while including the effects of bond-wires and surface mount PCB devices. Packaging limitations and die constraints can be taken into account early in the design process. This avoids after-the-fact design problems that can result from oversimplified off-die load models, and eliminates the painful debugging process of trying to fix them.

Chip/package/board simulations

In addition to a UDM for concurrency and co-design, powerful simulation technology is needed that can analyze the diverse set of component models comprising signal integrity data links. Figure 4 depicts this need schematically.

Figure 4. Gigabit applications involve modeling a chain of components.
(Click on image to enlarge.)

Transistor-level IC models are needed for accurate I/O buffer and serializer/deserialer (SERDES) phase locked loop (PLL) simulations. Transmission line and S-parameter models are needed for accurate package and interconnect simulations.

One of the very few circuit simulation products addressing this challenge is HSPICE® from Synopsys, Inc. For over 25 years, HSPICE has been the standard in IC circuit simulation. All major foundries provide HSPICE transistor models for sign-off simulation, and chip vendors provide either IBIS or triple-DES encrypted netlists for HSPICE simulation.

The IC-level modeling support of HSPICE is therefore considered the most validated and trustworthy SI solution available. In addition, HSPICE provides two significant technologies for modeling off-chip components: a generalized modeling capability for lossy coupled transmission lines, and the ability to perform simulations directly from S-parameter data sets.

Coupled transmission lines are modeled in HSPICE using an approach based on distributed RLGC matrices referred to as the W-element. The approach is very general and applicable for most interconnect systems, due in part to the ability to represent any number of coupled interconnects, and an ability to handle substantial frequency dependence. Any system of uniform coupled transmission lines can be characterized with RLGC matrices.

Unlike the RLCG models of the past that map to simple lumped-element equivalents, RLGC matrices represent a complete mathematical description of the complex distributed propagation characteristics of coupled transmission line systems. Matrix values can be derived from physical trace geometry, using electromagnetic field solvers (such as HSPICE's built-in 2D EM solver), or by converting from the propagation and impedance parameters used in board-level transmission line component libraries.

Frequency-dependent RLGC matrix values are critical for modeling GHz loss effects due to skin effect (conductors) and loss tangent (dielectrics). Interconnects also possess dispersion at GHz frequencies, resulting in frequency-dependent propagation factors, which are also captured as RLGC frequency dependence. Such methods have allowed W-element models to align with measured data at frequencies as high as 40-110 GHz.

But the most impressive aspect of the W-element is its ability to provide fast and accurate time-domain simulations. Most tools that use frequency-domain models for time-domain simulation employ convolution calculations that are notoriously slow. The W-element, however, uses techniques that efficiently separate propagation, reflection, and loss factors, enabling fast recursive convolution while ensuring causality and passivity.

S-parameters fuel successful SI design

S-parameters, also called scattering parameters, have become the preferred method for characterizing passive components which are not well modeled by SPICE or transmission line methods. S-parameter data sets may originate from EM simulation, from direct vector network analyzer measurements, or from a linear circuit simulation of portions of an SI link. There is a definite trend towards encapsulating much of the off-chip design into a few large S-parameter data sets. In the case of IC package models, very large S-parameter data files may be involved. Efficient handling of such data has therefore become a priority for SI simulation.

The HSPICE S-element allows S-parameter data files to be used directly for simulation. Convolution calculations are performed automatically for time-domain simulation. Several options are available for handling S-parameter data in the most efficient ways possible. For large data files used to represent IC packages, HSPICE generates reduced order models (ROM) that can be efficiently analyzed with recursive convolution.

When S-parameter data is available for transmission lines, the data can be used as input for specifying a W-element model (Figure 5).

Figure 5. HSPICE supports several options for S-parameter data input, including the ability to extract W-element transmission line models from scattering parameter data.
(Click on image to enlarge.)

Transmission-line propagation and RLGC values are then calculated automatically, allowing the W-element to apply fast recursive convolution calculations for time-domain simulation. HSPICE includes a variety of advanced sS-parameter data interpolation and extrapolation schemes to handle things such as proper behavior at DC (zero frequency), insufficient data sampling at resonant frequencies, and smoothing for noisy measurements.

A solution based on a unified data model, combined with the SI simulation strengths of HSPICE, offers unique design flow advantages to meet the needs for multi-Gbps SI design and simulation. The design software adaptively maps complete chip/package/board links into simulation-ready HSPICE models. For distributed elements, models can be mapped from a passive element library validated for microwave applications, up to and beyond 100 GHz, into the HSPICE W-element for single schematic co-simulation in frequency- and time-domains.

The HSPICE software also includes a special interface layer for rational function approximations of S-parameter data sets. Using Foster's canonical form, the interface enforces passivity and guarantees causality for HSPICE time-domain simulation, whether directly from S-parameter data files or the result of integrated, concurrent EM analyses within the design suite. This, combined with HSPICE's trustworthy IC device and IBIS models, provides a comprehensive chip/package/board signal integrity simulation solution. High data-rate signal paths can be designed with on-chip and off-chip awareness, and then taken to fabrication by exporting to enterprise PCB tools.


The design of next-generation, high-performance communications products requires the consideration of complex cross-domain SI issues. This paper has outlined a modern SI design methodology that utilizes a top-down approach to IC, packaging, and PCB SI, enabling engineers to meet the challenges presented by multi-Gbps design issues. This approach solves many SI issues early in the design phase, prior to analysis, saving design iterations and shortening time-to-manufacture.

About the authors
Scott Wedge, Ph.D ( is a senior staff engineer with Synopsys Corporation. He has authored numerous technical papers on RF/microwave theory and design, is a former Howard Hughes Doctoral Fellow, and holds two patents in RF/microwave technology.

Mike Heimlich, Ph.D ( is the microwave market segment director for Applied Wave Research, Inc. He has published papers in many technical journals and proceedings on MMIC and module design and EDA tool integration, and holds a patent in EDA tool integration.

FPGA-Based Prototyping - "Productivity to Burn"

FPGA-Based Prototyping - "Productivity to Burn"

This article highlights recent tool advances that can help you setup, implement, and verify your FPGA-based ASIC prototype faster than ever before.

Programmable Logic DesignLine

These days, a large portion of ASIC, SoC, and ASSP designs are at least partially prototyped in one or more FPGAs. This amounts to many thousands of prototyping projects per year. Compared with other ASIC verification methods, however, FPGA Prototyping is mistakenly seen by many as an ad-hoc mix of tools that must be cobbled together by hand. In reality, powerful integrated tools, platforms, and expertise exist that greatly improve the productivity of FPGA-based ASIC prototyping. This article highlights recent tool advances that can help you set-up, implement, and verify your prototype faster than ever before.

Prototype setup

Use the right FPGAs
ASIC designs are generally larger – and often faster – than FPGA Devices, and they tend to push the envelopes of FPGA performance and density. Thus, we will almost always be using the largest FPGAs (in the fastest speed grade) available. Anything less might seem to save money, but in the end could make timing closure harder to reach or make the design harder to fit (or both).

Less obvious is the fact that we should also use the device in a package with the most available I/O pins and with the most flexible support for clocking, voltage, and I/O standards. The I/O often becomes the most valuable resource on the devices, especially when designs are partitioned across multiple FPGAs. Synplicity builds HAPS (High-Performance ASIC Prototyping System) boards using the largest Xilinx devices – namely the Virtex-5 LXC5V330 in the -2 speed grade and the 1760 ball grid array package.

Design partitioning
If a design takes up more than 70% to 80% of the largest FPGA available to you, then it is worth considering partitioning it across more than one device. Some designs have natural and obvious partitions based on existing hierarchical boundaries. The aim is to ensure that we do not create new critical paths in the design that cross between FPGAs on the board.

In order to address this, Synplicity's Certify tool has numerous partitioning aids from low level block zippering up to completely automatic full-RTL partitioning. These allow as much or as little manipulation of the design as required to meet the performance goals, but all involve no changes at all to the original ASIC RTL.

An important manipulation of the design that Certify can perform without changing the RTL is to automatically add I/O pin multiplexing between FPGAs. This uses time-sharing of the wires between the FPGAs so that they carry two or more signals, thereby alleviating potential I/O bottlenecks which often arise at the partition boundaries.

Many of Certify's partitioning aids have been developed to meet the needs of users performing hundreds of partitioning projects within major Semiconductor and System labs since 1999.

RTL manipulation
ASIC designs often contain design features that are FPGA-Hostile. For example, ASIC designs are typically sprinkled with instantiations of elements or macros from ASIC technology libraries or macro generators. This leaves "black-box" holes in the RTL for which some functionality must be described in order to complete the FPGA implementation. Some of this functionality is provided automatically by Certify, which can extract the required RTL from the ASIC library itself. Synopsys DesignWare instantiations are dealt with automatically in a similar way.

Another FPGA-hostile facet associated with many ASIC designs is their complex clocking structures. Multiple clock domains, asynchronous parallel channels, and gated clocking trees will quickly overflow the global synchronous clock resources of even the largest FPGAs. Certify will automatically simplify gated or generated clock networks back to a common system clock and build the required enable signal to ensure equivalent functional behavior. An example of this is shown in Fig 1. The result is to match to the resources available inside the FPGA.

1. Automatic gated clock conversion.

Implementation and verification

Fast design iterations
Implementation is a critical phase in the FPGA prototyping flow. The partitioned design may undergo many iterations as bugs are discovered and fixed, or design blocks are tweaked and re-tweaked for higher performance.

It is very important to keep this iteration loop as short as possible. However, the combination of leading-edge ASIC designs in the multi-million system gate range, and stretch performance goals to model real-world operation, can lead to lengthy synthesis and place-and-route passes. The great advantage that FPGAs offer for debugging and design exploration begins to diminish when using traditional FPGA flows and large design sizes. The answer is to use incremental implementation methods.

Xilinx's ISE 9.2i design software offers a technology called SmartCompile which is ideal for the ASIC prototyping flow. Designed to speed up the implementation flow by 2-to-6 times versus traditional flows, SmartCompile is comprised of three components: SmartPreview, SmartGuide, and Partitions (not to be confused with multi-FPGA Partitioning).

SmartPreview allows you to halt the ISE tool flow in mid-stream to see how a particular implementation pass is proceeding. While halted, you can check key implementation information like the number of timing violations, the timing score, or the number of constraints met so far. You can even save the intermediate design and timing reports and create a bitstream for lab debug. If the implementation is proceeding as expected you can resume the pass; or you cancel a run that is not proceeding as planned, thereby saving valuable design time.

SmartGuide delivers automated incremental design to the FPGA design flow. SmartGuide can speed up the implementation phase by 2-to-6 times depending on design size and hierarchy setup.

With SmartGuide turned on, your first full implementation run is "guided", or marked for component and route placement. Let's say after a debug session you decide to make a design tweak and change one HDL source. As you re-enter the implementation flow, SmartGuide examines the hierarchy and identifies where the design needs to be re-implemented. Where possible, SmartGuide will reuse the placement and routing that didn't change from the prior implementation pass, thereby speeding up the re-implementation flow (sometimes dramatically).

Synplicity and Xilinx have collaborated closely, as part of our Timing Closure Task Force, to enforce name consistency in both tools. This means that names remain constant from run to run of the Synthesis and Place-and-Route, thus ensuring best possible guided flow results.

Some incremental tool flows can produce worse timing paths from having to route around "locked" modules, but SmartGuide has the ability to identify critical timing paths and – if necessary – free up portions of an otherwise unchanged module for re-implementation, emphasizing critical paths and keeping timing a priority.

The third component of SmartCompile is Partitions, which offers the ability to completely lock down a completed module's placement and routing. In this way, a debugged "known-good" module or piece of purchased IP can be implemented and then set aside while you concentrate on debugging your other modules, while still enjoying the benefits of an incremental implementation flow. Partitions can be locked down early in the tool flow by using Compile Point Technology within the Synplify Pro and Synplify Premier synthesis tools. The partition information is automatically passed on to ISE.

All the components of SmartCompile work directly with either Xilinx or Synplicity synthesis and can cut the implementation flow for large designs by between 2 and 6 times. SmartCompile delivers more time for critical module debug, thereby freeing the engineer from watching lengthy and cryptic synthesis and place-and-route runs.

This is typically where the majority of your time is spent on a prototyping project. The ability to debug any portion of the design quickly and accurately is critical to project success. Let us consider two methods for embedding Virtual Logic Analyzers into the design so as to allow logic and embedded software designers to debug their FPGAs in real time. The two methods are Chipscope Pro from Xilinx and Identify Pro with TotalRecall Technology from Synplicity.

ChipScope Pro
With the ChipScope Pro system – which is available as a separately purchased option to Xilinx ISE software – design problems can be quickly found while the chip is running on the board and interacting with the rest of the system. Then, leveraging the FPGA's re-programmability, design changes can be quickly implemented and sent back to the device on board in a matter of minutes through the FPGA programming cable.

The ChipScope Pro package of tools includes a set of configurable and synthesizable software debug cores that are either instantiated into your FPGA design during HDL capture or inserted directly into the project netlist (Fig 2). Following implementation, using these cores you can view any internal signal within the FPGA.

2. ChipScope Pro core insertion options.

Signals are captured at or near operating system speed and then brought out through the programming interface, thereby freeing up pins for your design as opposed to gobbling them up for debug. And ChipScope Pro is one of the only tools that allow you to change probe points without having to re-synthesize and re-route your design. Using the ISE FPGA Editor, you can change signal probe points and then quickly reprogram your FPGA and debug a whole new set of signals in a matter of minutes.

You can analyze captured signals through the ChipScope Pro software logic analyzer. This is an advanced display and debug tool that makes logic and embedded bus analysis easy. The ChipScope Pro logic analyzer supports multiple window views, and bus plotting can be in either data-versus-time or data-versus-data formats. Capture mode lets you compare data captured after multiple trigger events; meanwhile signal filtering lets you ignore data that's not critical to your analysis, thereby saving you memory and analysis time. Using the listing viewer, you can import bus token files and view instructions in the order they occur.

To facilitate processor system debug environments that use software debuggers in addition to ChipScope Pro tools, you can share the JTAG connection to the FPGA with the ChipScope Pro analyzer.

In addition to providing data capture capabilities, the ChipScope Pro system also includes the Virtual I/O console, the interface to the industry's first real-time virtual input/output core. Through the Virtual I/O console, you can set virtual inputs and pulse trains and view output activity.

ChipScope Pro tools can run in server/client mode over a TCP/IP connection. You can sit in your office while debugging a board next door in the lab or on the other side of the world. You can share a single prototyping board in the lab with other debug engineers on your team.

Identify RTL Debugger
Going beyond beyond the functionality of ChipScope Pro, Synplicity's Identify tool makes is possible to perform the on-chip debug at multiple hierarchical points within the RTL source and to do this without altering the source at all. Identify uses an automated instrumentation technique in order to create and attach sampling, trigger and communication logic into each FPGA forming the prototype as required.

Waveform views such as those seen in the ChipScope Pro logic analyzer are possible, but a significant added bonus is that the samples and triggers are overlaid onto the RTL source code using the same symbolic names as in the RTL. Thus, for example, it is possible to see the actual value of an enumerated type in which a state machine is captured on the FPGA. Triggers may be set in a similar way, using the source name-space. A unique benefit is that triggers can be set for when a particular line of RTL is reached, much like a software engineer would set breakpoints in a program.

Identify Pro with TotalRecall Technology
Newly available in a superset of Identify – called Identify Pro – is Synplicity's TotalRecall full visibility debug technology (see also Programmable Logic DesignLine article 196801895 titled How to achieve 100% visibility with FPGA-based ASIC prototypes running at real-time speeds).

Whereas ChipScope Pro and Identify rely on sample points to be set in advance, Identify Pro with TotalRecall provides visibility into the entire design. This allows the automatic extraction of a testcase from the FPGA and rerun in a standalone simulator. Upon a trigger occurring in the FPGA, the full status of the module under test (not just certain sample points) is captured as it was many thousands of clocks BEFORE the trigger occurred.

This module state is extracted and converted for use in the users' own simulator. A significant advantage is that the testbench for the simulator is also extracted from the FPGA, so that the module under test is re-stimulated with the actual inputs it had received from the point at which the module's state was captured, right up to the point at which the trigger occurred.

Once in the simulator, the full suite of analysis tools including single-step, force, freeze etc. can be brought to bear. The prototype is freed up for further verification task while the simulation takes place.

Summary – putting it all together
In conclusion, significant and continual progress in FPGA devices, Synthesis, Place-and-Route tools, and debug capabilities has made FPGA prototyping much more accessible and useful to ASIC verification teams than ever before.

Observability and controllability have been added to the already unchallenged superior performance of FPGA prototypes to offer cheap, fast platforms for RTL debug and software integration into real world test environments. If you are ready to explore the benefits of FPGA Prototyping, Synplicity and Xilinx are ready to help you to prototype your project.

Xilinx offers the most advanced silicon, software, and support available in FPGA prototyping, while Synplicity has created a complete prototyping environment – called the Confirma Platform – which includes leading prototyping hardware based on Virtex-5 FPGAs and the EDA tools mentioned in this article. For more information, go to or



Monday, January 28, 2008

Tackle team-based FPGA design

Tackle team-based FPGA design

You see them at almost every user seminar or industry trade show workshop: the Methodology Managers from XYZ Corporation, who describe the system they use to help the company make sense of the intellectual property (IP) produced by their design teams. And it's got to be a daunting task--development staff working in different time zones; language barriers; software tool versions to track and synchronize; VHDL/Verilog/C/C++, CAD databases. All of these (and more) diminish the reusability of any design module. You can respect the role these managers play and envy the sanity they bring to the organization.
But XYZ Corporation is a large company. How does a small or midsize firm like yours grapple with this imposing housekeeping chore?

Distributed design teams happen. With the right mix of specialty tools and culture, it's becoming more practical to create and manage distributed FPGA design teams by using modular FPGA design methods that allow multiple designers to work on parts of a single design independently.

Collaborative design
The benefits of collaboration are intuitive enough. Use the best people for the job, no matter where they are. Assign more people to the project when the schedule or feature set isn't flexible (and they seldom are). And, ideally, a natural and beneficial consequence of a partitioned design task is that FPGA building blocks (or IP modules) are created that can be reused for enhanced for derivative products.

Sometimes collaboration is imperative, if only because the one person knowledgeable about a particular task is in a different time zone from everyone else. Just as software teams might use a driver or GUI specialist, FPGA design teams might include a high-speed I/O specialist, a DSP designer, and a guru who knows the tools and the ins and outs of timing closure.

The scale of the designs intended for high-capacity FPGAs creates a formidable, likely impossible, demand for one or two design engineers to deliver the required content. It's often necessary to assign multiple engineers to the job.

FPGA design tools haven't provided much support for partitioning design work across multiple engineers until recently. Advances in FPGA design planning and place-and-route (PAR) tools, however, now help support a modular design style and complement synthesis and simulation tools that have traditionally supported design teams. Contemporary FPGA design tools are more aware of modular IP, can accommodate distributed development, and are focused on high-capacity devices.

Modular FPGA design
Modular FPGA design is an approach that enables multiple designers to work independently on parts of a single design. In this approach, a lead designer creates the top-level design; the rest of the design team works on constituent designs that will be merged into one cohesive design in the final assembly stage.

All major FPGA vendors now support a modular implementation strategy. Altera's LogicLock, Lattice Semiconductor's Block Modular Design method, and Xilinx's Modular Design Flow all provide strategies and tools that support partitioning, independent implementation, and assembly of design modules.1, 2, 3

Figure 1 illustrates an FPGA design partitioned across a team. The convention for most FPGA tools today is to allocate a branch of the design hierarchy to a team member, along with some "budget" for timing and device resources. That engineer can then establish a logical user hierarchy to whatever degree is appropriate for that design module.

Device-resource budgeting is a recent advancement in FPGA implementation tools that makes it possible for a subset of the design to be implemented independently of other design modules. A distinct advantage of this block-style flow is the ability to update the logic in any of the blocks while preserving the placement and performance of the surrounding blocks. The block-style flow enables the design tools to focus on new blocks or those that are changed. Being able to isolate and work on individual blocks shortens potentially long run times since, given a smaller design problem, PAR tools will typically produce better results sooner. Individual blocks can be implemented and updated separately, enabling quicker iterations and a more rapid path to design closure. In some cases, blocks can be reused in other designs, further leveraging resources and shortening those design cycles. From the perspective of a team collaborating on an embedded system, this makes future revisions of the platform more straightforward and faster to expand or modify.

Team-based design naturally works best for larger designs that can be easily partitioned into self-contained regions of the chip. Thorough preliminary planning, iterative experiments, and explicit, deliberate, and clear communication among design team members are all essential to ensure the partitioned designs work together in the final assembly step of the process.

Of course, partitioning the design presents challenges as well as benefits. For example, if the design architect's initial floor plan doesn't budget enough resources for a certain module, some sort of refinement loop is needed so a team member can negotiate for more room. Timing objectives also are likely to be handed down to team members and may not be as easily met as those for a design that is not floor-planned. The design architect must account for the availability of features such as high-performance embedded memories, DSP functions, and high fan-out routing spines because these anchor and size regions for each block. Given that contemporary FPGA architectures are a mixture of programmable fabric and rows of embedded functions, it can be awkward to create a block diagram that nicely accommodates the design logic. In this regard, modular design both benefits and suffers from a handmade floor plan where placement algorithms are constrained by the borders of each block.

What follows is a typical procedure for modular FPGA design that's common among the leading FPGA vendors. Figure 2 illustrates a typical data flow in a modular FPGA design

1. Partition the top-level design and synthesize design modules

Create a top-level design, along with constituent design modules, in HDL. The top-level design serves as the design documentation and is also the first opportunity to influence the performance results of the design. By using FPGA-friendly design-partitioning principles, you can dramatically reduce overall design time by simplifying the coding, synthesis, simulation, floor-planning, and optimization phases of the design. Here good guidelines include:

• Sub-blocks should be synchronous with registered outputs. Registering outputs helps the synthesis tool implement the combinatorial logic and registers into the same logic block. Registering outputs also makes the application of timing constraints easier, since it eliminates potential problems with logic optimization across design boundaries.

• Related combinatorial and arithmetic logic should be collected into the same design module. Keeping related combinatorial terms and arithmetic in the same design module allows sharing of logic hardware resources. It also allows a synthesis tool to optimize the entire critical path in a single operation.

• Separate logic with different optimization goals. Separating critical paths from non-critical paths will make logic synthesis more efficient. If one portion of a design module needs to be optimized for area and a second portion needs to be optimized for speed, those portions should be separated into two design modules.

As this top-level partitioning is underway, team members are also (in theory) modeling design modules. The order of operation isn't so important here, as long as each design module will eventually comply with the architect's top-level connections and organization. Even without a clear picture of the FPGA resources needed to implement all design modules, the team at least has the luxury of simulating and verifying the function of any combination of design modules by mixing register-transfer-level (RTL) logic with gate-level logic.

2. Create a floorplan, place blocks, and optimize

This step is the most critical one in the process. It includes area budgeting and reserving space in the top-level design for constituent blocks, determining I/O for each block along with the device's external I/Os, and determining the position of each block relative to the others.

FPGA design tools ease block floor planning with the following utilities:

• A schematic view of the register-transfer-level description (RTL) will help you view the data paths of the design along with the relative order of design modules. This view makes it obvious where blocks should be located relative to external I/Os.

• An abstract graphical floor plan view is used to size and anchor blocks. Once blocks are defined to hold one or more design modules, logical connections can be shown as "flywires" superimposed on the device resource floor plan. Heavily interconnected blocks will be placed adjacent to one another, while covering enough physical resources to accommodate the design logic.

Some systems allow you to direct which side of the block the logical interconnect will enter or exit to help define the data flow. Commonly recommended guidelines for this step include:

• Lock global logic resources like PLL/DLL-driven clocks and the external I/O plan. The floor plan should also define optimal positions for global logic such as clock drivers (whether they are programmable I/Os or embedded PLL/DLL) and external signals, with an eye toward signal types and the device's package organization. FPGAs may provide specialized I/O drivers for double-data-rate (DDR) or serializer/deserializer (SERDES) interfaces at specific locations of the device package, so you must account for these locations in the block floor plan.

• Define design module timing objectives. Performance objectives are defined by assigning physical and timing preferences in the respective FPGA synthesis tool.

• Place and orient blocks. At this point, you will budget device resources such as lookup tables (LUTs), registers, and memory or DSP elements by reserving a region (or block) of the floor plan. The resources allocated can be handled in a top-down manner based on rough estimates, or bottom-up based on the actual results produced by logic synthesis of a block. It's essential that the block's region is large enough to accommodate the design module's logic and allow for adequate I/O resources. The relative position and orientation of the blocks will depend largely on the device's internal interconnect. Modern FPGA tools provide floor-planning utilities to help visualize block interconnect and the physical resources available.

Ideally, this step is done in parallel with logic synthesis to help size the regions. This is almost always an iterative process because it's unlikely you'll get the floor plan right the first time. Some FPGA systems will automatically size regions based on logic consumption and allow blocks to include or exclude other logic, depending on resource needs.

3. Block-level PAR

This step implements each block with the top-level design constraints applied. This step must be completed before final assembly can be performed and is done in parallel with Step 2 but requires that the top-level floor plan with region constraints be completed.

Successful block implementation will depend largely on the preferences assigned for area budgeting and reservation and I/O placement determined in the previous step. If incorrect, repeat Steps 3 and 4.

The HDL design files for each block are generally synthesized into Electronic Design Interchange Format (EDIF) netlists. The FPGA software then imports the EDIF files. This step is required for all team members. The synthesis can be performed in any order.

4. Top-level assembly

In this final step, merge all the blocks into one cohesive design. The top-level design file must be configured and all blocks implemented before the design can be assembled. Successful assembly depends primarily upon the decisions made in Step 3 and the successful implementation of all constituent blocks.

Design example
This design example illustrates the application of modular FPGA design by a development team charged to implement a large communications design. The modular approach was an attractive means to partition, implement, and stabilize a significant portion of the design.

For the team creating a reference design demonstrating an orthogonal frequency-division multiplexing (OFDM) application, the objective was to establish timing and resource use for a major design module, which served as the Viterbi algorithm. The design module was targeted for a particular block/region of the floor plan composed of programmable function units (PFUs) and embedded block RAM (EBR). The team observed that overall PAR time decreased significantly versus the entire flattened design. In this case, the FPGA implementation tool treated block region resources as sharable, which allowed the top-level PAR phase to take advantage of the unused resources of the block region allocated for the design block. This was useful because the Viterbi module relied on both EBRs and a number of PFUs, but a side effect of rectangular block regions meant the architect had to enclose more EBRs in the block region than it practically needed. At assembly time, however, a top-level FFT block was able to use the excess EBRs.

The moral of the story for this team's partition effort was not to make more blocks than absolutely necessary in order to avoid over-constraining the layout. Since only one block was defined, the data path was not locked and the remaining "floating" logic naturally landed next to related logic of the block.

This project was a success story for the modular design technique. The team concluded that modular design would be highly useful when using IP blocks for the sake of standalone PAR. Modular design permitted timing closure of the Viterbi block in one step, and then the remainder of the design logic during assembly, leaving PAR results of the Viterbi block stable.

Going modular
New modular FPGA design techniques provide major advantages to distributed design teams. Portions of an entire design can be approached independently, allowing multiple designers to work in parallel. Working in parallel enables the application of additional resources, as necessary, to particular design modules.

Functional modules can be analyzed separately. This affords you a better vantage point from which to debug or enhance designs, because design problems can be traced to a specific portion of the design.

The timing of each constituent functional module is preserved because each module can be assigned to a particular region on the device, and the tools are constrained to use resources from that region.

The modular flow can be used for performance optimization and preservation: it can be used to place modules into regions in a device's floor plan. Because modular assignments are generally hierarchical, teams have more control over the placement and performance of modules and groups of modules. Typically, a block's region size, state, width, height, and origin can be modified.

All the leading FPGA vendors provide some type of a modular design method that follows a typical procedure of partitioning, floor planning, block implementation, and assembly.

Troy Scott has been helping design, document, test, and promote EDA products for about 14 years. He is a product marketing engineer at Lattice Semiconductor Corporation. Troy holds a BSCE from Oregon Institute of Technology and a Graduate Certificate in Computer Architecture and Design from Portland State University. He welcomes feedback and can be reached at

Endnotes:1. Altera's LogicLock:
2. Lattice Semiconductor's Block Modular Design method:
3. Xilinx's Modular Design Flow:

Design a clock divide-by-3 circuit with 50% duty cycle

The basic insight was to notice that if you are doing a divide by 3 and wanna keep the duty cycle at 50% you have to use the falling edge of the clock as well.
The trick is how to come up with a minimal design, implementing as little as possible flip-flops, logic and guaranteeing glitch free divided clock.

Most solutions that came in, utilized 4 or 5 flip flops plus a lot more logic than I believe is necessary. The solution, which I believe is minimal requires 3 flops - two working on the rising edge of the clock and generating a count-to-3 counter and an additional flop working on the falling edge of the clock.

A count-to-3 counter can be achieved with 2 flops and a NOR or a NAND gate only, as depicted below. These counters are also very robust and do not have a "stuck state".

The idea now is to use the falling edge of the clock to sample one of the counter bits and generate simply a delayed version of it.
We will then use some more logic (preferably as little as possible) to combine the rising edge bits and falling edge bit in a way that will generate a divide by 3 output (with respect to out incoming clock).

The easiest way (IMHO) to actually solve this, is by drawing the wave forms and simply playing around. Here is what I came up with, which I believe to be the optimal solution for this approach - but you are more than welcome to question me!

and here is also the wave form diagram that describes the operation of the circuit, I guess it is self-explanatory.

One more interesting point about this implementation is that it does not require reset! The circuit will wake up in some state and will arrive a steady state operation that will generate a divide by 3 clock on its own.

Thursday, January 3, 2008

List of Company Addresses

List of Company Addresses
X-Vision Software
945, 24th Main
IInd Phase, J.P.Nagar
Bangalore - 560 078
Phone: 646634

Worldscope Disclosure India Pvt. Ltd.
106, First Floor, Gandhi Bazaar Road
Bangalore - 560004

Wishbone Systems Pvt. Ltd.
968, 12th Main Road
HAL II Stage
Bangalore - 560 008
Phone: 5276717 Fax: 5276717

Wipro Systems Ltd.
3rd Floor, S.B.Towers
No.88, M.G.Road
Bangalore - 560 001
Phone: 5586202, 5588583 Fax: 5587984

Wipro InfoTech Group
88 MG Road,
Bangalore - 560001
Phone: 5588422
Fax: 5586657

Wipro GE Medical Systems
Plot No. 4, Kadugodi Indl. Area
Bangalore - 560057
Phone: 8452923/25/26

Visual Engineering Services (I) Ltd.
A-313, Block III, KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore - 561229
Verifone India Pvt. Ltd.
Indian Express Building
Dr. Ambedkar Road
Bangalore - 560 001
Phone: 2269920, 2269924 Fax: 229938

Unitech Systems (India) Pvt. Ltd.
III Floor, Classic Court
9/1, Richmond Road
Bangalore - 560 025
Phone: 2216442

Ultra Business Machines
II Floor, St. Patrick's Complex,
157 Brigade Road,
Bangalore - 560025
Phone. : 5585618/983
Fax: 5588626

Trigent Software Ltd.
620, 80 Feet Road
8th Block, Koramangala
Bangalore - 560 095

Thompsum Technologies (P) Ltd.
No. 29, Beratina Agrahara
Singasandra Post, Hosur Road
Bangalore - 560 068
Texas Instruments (India) Pvt. Ltd.
71, Millers Road
Sona Towers
Bangalore - 560 052
Phone: 2254235, 2259007
Fax: 2257024

84, IInd Main, Indranagar
Bangalore - 560 038
Phone: 5581986 Fax: 5581968
Tektronix India Ltd.
Tek Tower, Hayes Road,
Bangalore - 560025
Phone. : 2275577
Fax: 2275588

Tata Information System Ltd.
Golden Enclave Tower 'B'
Airport Road
Bangalore - 560 017
Phone: 5262355, 5267117, and 5269299
Fax: 5587374, 5583344, and 5587413
Tata Elxsi (India) Ltd.
No.123, Richmond Road
Bangalore - 560025
Phone: 563956, 564872 Fax: 583168

Tangerine Geoscience
15/8, Primrose Road
Bangalore - 560025
Phone: 5580357

Synopsys Development India (P) Ltd.
C/o KAMG, 5th Floor
Shariff Chambers, 14 Cunningham Road
Bangalore - 560 052
Phone: 2204600 Fax: 2204300

Stem Logic
1281, 21st Main JP Nagar,
II Phase
Bangalore - 560078
Phone. : 649054, 647304
Fax: 647753

Squire Systems
57/9, Manipal Center, 47,
Dickenson Road,
Bangalore - 560042
Phone. : 5594477

Spectra Innovations India Pvt. Ltd.
Unit 5822, Manipal Center,
47, Dikenson Road
Bangalore - 560002
Phone. : 5588322, 5583977
Fax: 5586872

1st Floor, APS Trust Building
Bull Temple Road, N.R.Colony
Bangalore - 5589722 Fax: 5585092

Software Development Systems
85, Narayanappa Block,
RT nagar II Block,
Bangalore - 560032
Phone. : 551568, 5535874
Fax: 5531874
Siemens Information Pvt. Ltd.,
No. 29, Infantry Road
Bangalore 560 001
Phone: 5543547/48
Fax: 2212418

Siemens Communications S/W Ltd.,
Raheja Towers, 10th Floor
M.G Road
Bangalore 560 001
Phone: 5594067
Fax: 5594069

Sibcomm Technology (P) Ltd.,
A-308, Block III
KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore 561 229

Shankti Design Pvt. Ltd
5/5, First Main Road
Jayamahal Extension
Bangalore 560 046
Phone: 560 046

Search (India) Pvt. Ltd
Flat No. 211, Block III,
KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore 561 229
Phone: 2221987
Fax: 2239508

Samyog Software
"Saugandh" 476/A
13th Cross, 28th Main
1st Phase, J.P Nagar
Bangalore 560 078
Phone: 6614281

SPAN Systems
939, 23rd Main, 38th Cross
4th T Block, Jaya Nagar
Bangalore - 560041
Phone: 6639596 Fax: 6631304
SE Technology Ltd.,
A-205/206, Block III
KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore 561 229

Rothwell Systems Pvt. Ltd.
130/5, Infantry Road
Balaji Complex
Bangalore - 560 001
Phone: 576950

R & R Software
73, 1st Floor, 7th A Cross
4th B Block, Koramangala
Bangalore - 560 034
Phone: 534175

Processware Systems (P) Ltd.
33, Patalamma Temple Street,
Bangalore - 560004
Phone. : 6614163, 622188
Fax: 6629635

Premium Logic System Ltd.
No. 214, IInd Main Road
HIG House, RMV IInd Stage
Bangalore - 560094
Phone: 2212134

Premier Computers Consultancy Services
1/2, Krishna Road Basavanagudi,
Bangalore - 560004
Phone. : 621004

Pinero Ltd.
A-306, Block III, KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore - 561 229

Pharma Systems Pvt. Ltd.
199f, 27th Cross Road
7th 'B' Main, Jayanagar
Bangalore - 560 011

Peutronics Pvt. Ltd.
331-336, Raheja Arcade,
Bangalore - 560095
Phone. : 5533156
Fax: 5533986

Perpetyal Power Technologies
842 A, 100 Ft Road, Indiranagar,
Bangalore - 560038
Phone. : 5254315, 8520407
Fax: 5297706

OCS International Pvt. Ltd.
No. 863D, 12th Main
IIIrd Block, Koramangala
Bangalore - 560 034
Phone: 530649, 5534903 Fax: 5533022
Nuko Information (India) Pvt. Ltd.
B-110, Block III, KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore - 561 229

Novell Software Development (India) Ltd.
A.M. Industrial Estate No. 49/1 & 49/3
Garevebhavi Palya, 7th Mile Hosur Road
Bangalore - 560 068
Phone: 2219982/83 Fax: 2219929

Nobel Systems
6/1, Connaught Road
Queens Road Cross,
Bangalore - 560 052
Phone: 2266560, 2251040 Fax: 2256790

Netquest India Pvt. Ltd.
224/16, Ramana Maharshi Road
Bangalore - 560 080
Phone: 3312966, 3312967

NATSEM India Designs Pvt. Ltd.
1014 First Floor
3rd Cross, 13th Main, HAL 2nd Stage
Bangalore - 560 008
Phone: 5262110, Fax: 5543369

Multimedia Station Inc.
501, 5th Cross,
HMT Layout, Ganga Nagar
Bangalore - 560032
Motorola India Ltd.
108, Gavipuram Guttahalli,
Off Bull Temple Road,
Bangalore - 560019
Phone: 6612973/4/5
Fax: 6612977

Motorola India Electronics Pvt. Ltd.
Presidency, No. 1, St. Marks Road
Bangalore - 560071
Phone: 2218545 Fax: 2210841

Motor Industries Co. Ltd. (MICO)
Hosur Road, Adugodi
Bangalore - 560 030
Phone: 2220088 Fax: 2212728

Microland Ltd.
58, 80 Feet Road,
Koramangala Block 7,
Bangalore - 560095
Phone: 5534340
Fax: 5534992

Microcon Instruments and Systems
722/22 10th A Main Road
4th Block, Jayanagar
Bangalore - 560 001
Phone: 6633862 Fax: 6633862

Mentor Systems Solutions Pvt. Ltd.
5th Floor, AI-Tower
Golden Enclave Airport Road
Bangalore - 5263615, 5263751
Fax: 5586606

Menon Information Technology
No. 20(32), Lakshmi Towers
R.V.Road, Basavanagudi
Bangalore - 560 004
Phone: 3312528 Fax: 3312528

Macmet India Ltd.
40, Langford Road
Bangalore - 560025
Phone: 2238699 Fax: 2213984
Telex: (0845) 8152 MCMT

Linc Software Service Pvt. Ltd.
C-211, Block III, KSSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore - 561 229

Learn Soft
1 Floor Venkatadri Complex,
83, Richmond Road,
Bangalore - 560025
Phone. : 2217350, 2243616

LEC India Software Center (P) Ltd.
12th Floor, DU Parc Trinity, M.G.Road
Bangalore - 560 001

Kirloskar Multimedia Ltd. Cresent Towers, No.32/1 & 32/2 Cresent Road, High Grounds
Bangalore - 560 001
Phone: 3363357 Fax: 2200016
Kirloskar Computer Services Ltd.
P.B.No. 5570, Malleswaram West
Bangalore - 560 055
Phone: 3322280, 3322082, 3322583

Kiefer & Vettinger Information Sys P Ltd.
Jayaram & Jayaram, 7/3, E Block, 1st Floor
Unity Building, Mission Road
Bangalore - 560 002
Phone: 2235264 Fax: 2223968

Intrak Software Systems Private Ltd.
702, 6A Cross, III Block
Bangalore - 560 034
Internet Systems (P) Ltd.
328/14, HBR Complex,
15 Th Cross, Jayanagar, II Block,
Bangalore - 560011
Phone. : 6639496
Fax: 6633706

International Computech Engg. Services
A-212, B-209/210, Block III, KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore - 561229
Intercope (India) Pvt. Ltd.
No. 41, 1st Cross, 3rd Main
Domlur 2nd Stage
Bangalore - 560071
Phone: 5278596 Fax: 5265351
Integra Macro Systems Pvt. Ltd.
G 5&6, Swiss Complex
No.33, Race Course Road
Bangalore - 560 001
Phone: 226007, 2267027 Fax: 2203928
Innovation Tech. Transfer (I) Pvt. Ltd.
1/5 Santosh Complex
Armugam Circle, Basavanagudi
Bangalore - 560 004
Phone: 6612226 Fax: 6612571

Information Mang. Res.(I) Pvt. Ltd.
Industrial Factory Building No. 38/1
Naganthapura Village, Singasandra Post
Bangalore - 561 221
Informatics Group
337, Karuna Complex, III Floor,
Sampige Road, Malleswaram,
Bangalore- 560003
Phone. : 3365940
Fax: 3367867

Indian Telephone Industries
Bangalore Complex, Dooravaninagar
Bangalore - 560 016
Phone: 8511211 Fax: 8511724

India Computer Center
11, King Street,
Richmond Town,
Bangalore - 560025
Phone. : 2215662, 2273921
Fax: 3320200

Imagine Information Technology Ltd.
No. 813, South Block, Eighth Floor
Manipal Centre, 47, Dickinson Road
Bangalore - 560 042

ITC Ltd.
B-309, Block III, KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore - 561229

IT Solutions India pvt. Ltd.
17, 3rd Floor, Southend Road
Bangalore - 6622153, 6617345, 6617346 Fax: 662154

IMR India Ltd.
38/4, Naganathapura Village,
Singasandra Post,
Bangalore - 560068
Phone: 5537691
Fax: 5532850

Honeywell Ltd.
Block III, KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore - 561 229

Hinditron Tektronics Instruments Ltd.
5, Crescent Road
High Grounds
Bangalore - 560 001
Phone: 2265470/71 Fax: 2250669

Hierarchial Object Oriented Dev. Comp.
Duplex Flats, A & C Chandra Apartments
82 Infantry Road
Bangalore - 560 001

Heuristix Systems Pvt. Ltd.
239/A-1, 10th Cross, RMV Extension
Bangalore - 560080
Phone: 3340496, 3346589, and 3341740
Fax: 5586287 Telex: (0845) 2696,8055

Health Scribe India (P) Ltd.
B-202/B-203, Block III, KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore - 561 229

Gulftech India Pvt. Ltd.
No. 2008, 100 Feet Road
HAL II Stage
Bangalore - 560 056
Phone: 5561672, 5585152 Fax: 5580101

Genesys Interactive Systems (I) Pvt. Ltd.
F-5, First Floor, Hall Mark Appartments
1 Wheeler Road, Fraser Towen
Bangalore - 560 005
Phone: 5542078 Fax: 5542078

Faculties India Systems Services
#14, 8th Main Road, Malleswaram
Bangalore - 560 003
Phone: 3349594 Fax: 3346185
Eurolink Overseas Pvt.
F-2, Block B-1
Mohan Co-op Industrial Estate
New Delhi - 110 044
Phone: 6948617, 6941831, 6941832 Fax: 6943732

Fidelio India Pvt. Ltd.
No.60, 4th Main Road
Domlur II Stage
Bangalore - 560 038
Phone: 5260691-93 Fax: 5260695

Esseven Infotech Ltd.
375, 1st Cross, 9th Main
Judges Colony, R.T.Nagar
Bangalore - 560 032
Phone: 3336730

Esseven Infotech Ltd.
289, 15 Main,
Bangalore - 560003
Phone. : 3312374, 3311730
Fax: 3311922

Equinox Solutions Pvt. Ltd.
130/1, Ulsoor Road
Bangalore - 560 042

Easi Technologies Pvt. Ltd.
204/C, 6th Main, 27th cross
III Block, Jayanagar
Bangalore - 560 004
Phone: 6631375 Fax: 6633888
EWI Engineers & Consultants (I) Pvt. Ltd.
C/o S.Rao & Co., Chartered Accountants, 300/1D
16th Cross Road, Upper Palace Orchards
Bangalore - 560 080
Phone: 3312528, 3313677 Fax: 3313679

EMpower India
No.414, I Cross, 7th Main Road
HAL II Stage
Bangalore - 560 008

EMRC Engineering Mechanics Research India (P) Ltd.
907, Barton Center,
84 MG Road,
Bangalore - 560001
Phone. : 5550298, 5594770, and 5586576
Fax: 5594770
Deutsche Software (India) Pvt. Ltd.
VIII Floor, Raheja Towers, 26-27, M. G. Road
Bangalore - 560001
Phone: 5596314, 5596320 Fax: 5597439

Deneb Hitech India Pvt. Ltd.
No.15, IAT Buildings
Millers Tank Bed, Queens Road
Bangalore - 560 052
Phone: 2205121 Fax: 564163

Decision Software India
26, Victoria Road
Bangalore - 560047
Phone: 560665, 579087 Fax: 226674, 2251468

Deccan Logitech Pvt. Ltd.
40, II Main, C.K.C. Garden
Mission Road
Bangalore - 560 067
Phone: 2224622 Fax: 2240866

DTA Software
3568/2, 4th Cross 15 th G main,
HAL, 2nd Stage,
Bangalore - 560038
Phone. : 5260921, 5261912
Fax: 5261911
DSM Soft (P) Ltd.
9, 15th Cross Street
Shastri Nagar, Adayar
Madras - 600 020
Phone: 4913878, 4911376 Fax: 4910847

DTA Software Pvt. Ltd.
15A, Kalpavriksha
12, Race Course Road, Madhavnagar
Bangalore - 560 001
Phone: 2261371 Fax: 2205469

DDMS Simulations S/W Consult Ltd.
657, 31st Cross, 11th Main
4th Block, Jayanagar
Bangalore - 560 011
Phone: 6634668 Fax: 6634229

DDE-ORD Systems Ltd.
29, Shanti Road, Shanti Nagar
Bangalore - 560 027
Phone: 2237674 Fax: 2236204

Cyber Systems
106, 1st Floor,
HAL II Stage,
Bangalore - 560075
Phone: 5283543
Fax: 5283543
Cyber Marketing
22, Koramangala Industrial Area
Bangalore 560091
Phone: 5534711
Fax: 5532427

Cranes Software International
No. 5, Airport Road,
Domlur Layout
Bangalore - 560071
Phone: 5549338
Fax: 5546299

Cosystems (India) Pvt. Ltd.
9/2, 6th Floor, Dhondusa Complex
Residency Road
Bangalore - 560 025
Phone: 2271852, 2240994 Fax: 2261468
Coromandel Solutions (P) Ltd.
(Since Changed To Intgra Technosoft Private Limited)
CSL House, 1 Cross I Block, Jayanagar
Bangalore - 560011
Phone: 6647924 Fax: 6654669

Complete Business Solutions (I) Ltd.
19, Annaswamy Mudaliar Road
Bangalore - 560 042
Phone: 560188 Fax: 560188

Client Server System
45/7, Vinayaka Complex
II Floor, Presidency Cross Road
Bangalore - 560 001
Phone: 5598421

Clearview Technologies Private Ltd.
280, 21st Main, I Phase, II Stage
BTM Layout
Bangalore - 560 076
Phone: 6640636

Chandra Chemical Enterprises Ltd.
A-312, Block III, KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore - 561 229

Celsuistech Systems
S-175, Block III, KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore - 561 229

Capsoft India Pvt. Ltd.
No.401, IVth Floor, Hoysala Apartments
Cunningham Road
Bangalore - 560 052
Phone: 2204724 Fax: 2204987

Cantech Infor. Systems Pvt. Ltd.
308, Brigade Gardens, 19 Church Street
Bangalore - 560 001
Phone: 5594397 Fax: 5594398

Calogic Technology India Pvt. Ltd.
63, Palace Road
Bangalore-560 052
Phone: 2202565 Fax: 2202565

Cadus International Pvt. Ltd.
A-203, Blue Cross Chambers,
11, Infantry Road Cross,
Bangalore - 560001
Phone. : 5598502, 5598743
Fax: 6610863

CG Smith Software Ltd.
1-A, Peenya Ind. Estate, Peenya
Phone: 8391663 Fax: 8391665

CCE Software
(A Division Of Chandras Chemicals Ent. Ltd.)
A - 312, Software Technlogy Park , III Block , KSSIDC Building
Hosur Road , Electronics City
Bangalore - 561229
Phone: 8520989 Fax: 5533022

Building Network Automation
146, Shantala Plaza,
VII Main, XIV Cross Malleswaram,
Bangalore - 560003
Phone: 3345451, 3341902
Fax: 3314313

Britannia Industries Ltd.
Airport Road,Vimanpura
Bangalore - 560017
Phone: 560065, 561749 Fax: 560355
Telex: (0845) 8575

Bharat Electronics Ltd.
Software Export Department
144, Shubharam Complex, Ist Floor, M .G. Road
Bangalore - 560013
Phone: 5582367, 5583853 Fax: 543675
Telex: (0845) 8485 SOFX IN

Baysoft Private Limited
No. 30, Church Street
Bangalore - 560001
Phone: 5598939, 5598940 Fax: 5598941

BAeHAL Software Pvt. Ltd.
Airport Lane, HAL Estate
Bangalore - 560017
Phone: 5275867, 5262927 Fax: 5270915

Autodesk Inc.
206, Raheja Plaza, 17, Commissarait Road
Shoolay Tank Bed Area,
Bangalore - 564939
Phone: 564928, 564939
Fax: 564897

Authorisation Systems (I) Pvt. Ltd.
No. 502 Westiminister, 43, Cunningham Road
Bangalore - 560 052
Phone: 2205114/ 2205839
Aspect-DCM Pvt. Ltd.
Leo Complex, Vth Floor, Residency Road Cross-
Bangalore - 560 025
Phone: 5585342/1267 Fax: 5585238

Arcus Technology Pvt. Ltd.
201, Embassy Chambers
No.5, Vittal Mallya Road
Bangalore - 560 001
Phone: 2217307 Fax: 2210336
Analog Devices India Pvt. Ltd.
4/2, Samrah Plaza, 1st Floor, St. Marks Road
Bangalore - 560 001

Ampersand Software Applications Ltd.
No. 68, 14th Cross, R.T. Nagar 1 Block
Bangalore - 560032
Phone: 3336173
Fax: 3333891

Altair Software India Pvt. Ltd.
A-109, Block III, KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore - 561 229

Advanced Micronic Devices Ltd.
65, Arun Complex, DVG Road Basavangudi
Bangalore - 560004
Phone: 600631, 605224, 607800, and 604502
Fax: 6608785 Telex: (0845) 8332MDBG IN
E-mail: 74022,
Aditi Technologies Pvt. Ltd.
224/16, Ramana Maharshi Road
Phone: 3312966, 3312967 Fax: 3346201

AL Information Technology
A-105, Block III, KSSIDC Multi Storied Complex
Keonics Electronics City, Hosur Road
Bangalore - 561 229
AI Soft Pvt. Ltd.
910, Brigade Towers, Brigade Road
Bangalore - 560025
Phone: 2218262, 2218263
Fax: 2215604

Mentors Systems Solutions Pvt. Ltd.
5 Th Floor, A1 Tower, Golden Enclave, Airport Road
Bangalore - 560017
Phone: 5263615, 5263751 Fax: 5261418

Manhattan Associates Software (P) Ltd.
657, 11th Main, 31 st Cross, 4th Block, Jayanagar
Bangalore - 560011
Phone: 6634668 Fax: 6634229
Infosys Technologies Ltd.
Plot No. 44, 3rd Cross
Electronics City, Hosur Road
Bangalore - 561229
Phone: 8520261/2/8520270 Fax: 8520361/2
Index Computing Pvt. Ltd.
Sharrif Chambers, 14, Cuningham Road
Bangalore - 560052
Phone: 2250689 Telex: (0845) 8555, 8992

Hewlett-Packard (I) Software Operations Pvt. Ltd.
No. 29 , Cunnigham Road
Bangalore - 560050
Phone: 2265595, 2261254/1554/1075/5931 Fax: 2200196

BPL Systems and Projects Ltd.
64, Church Street
Bangalore - 560001
Phone: 91 (80) 5586598, 5597389
Fax: 91 (80) 5586971

BFL Software Ltd.
45/3, Gopalakrishna Complex, Residency Road
Bangalore - 560025
Phone: 5588722 Fax: 5581918
Ashok Leyland Information Technology Ltd.
218/219, Raheja Chambers
12, Museum Road
Bangalore - 560001
Phone: 5587811, 5597924
Fax: 5584708

Advanced Synergic Microsystems Ltd.
80/2, Lussane Court, Richmond Road
Bangalore 560025
Phone: 2270547, 2274121/122
Fax: 2240548, 2273606
Telex: (0845) 2298 IFTK IN

Vishes Technologies
325, Chinmaya Mission Hospital Road,
Bangalore - 560038
Phone. : 560050, 565600
Fax: 5565090
Srujana Technology
1037, Dr. Rajkumar Road,
IV Block Rajajinagar,
Bangalore - 560010
Phone. : 3380710, 3303175
Fax: 3388074

Select Systems & Software (P) Ltd.
3050, 80 Ft Road,
HAL III Stage Indiranagar,
Bangalore - 560008
Phone. : 5281765
Fax: 5299033

SS Computers
Dugar House, 19,
Edward Road, Queen Road Cross,
Bangalore - 560052
Phone. : 2264884
Fax: 2255127

SRG Systems ( P ) Ltd.
35/3/A, Langford Road,
Bangalore - 560025
Phone. : 2233276, 2235246
Fax: 2218781
Ramsoft Technologies
4/1, XXII Cross-, VIII Main,
III Block, Jayanagar,
Bangalore - 560011
Phone. : 647152, 648102
Fax: 6631303

Nashsoft Systems
41, Lavelle Road,
Bangalore - 560001
Phone. : 2213345, 2271655
Fax: 2271657
Narmatha Electronics Centre
55, 13 A, Main Road,
Bangalore - 560050
Phone. : 6019116
Inventa Software (India) Pvt. Ltd.
2, Nandidurg Road,
Benson Town,
Bangalore - 560046
Phone. : 3333427, 3335549
Fax: 3336026

Encompass Software & Systems
129, Silver Lake Terrace,
167, Richmond Road,
Bangalore - 560025
Phone. : 5584068, 5584866
Fax: 5574322

Dharma Computers
#94, 4th B Cross Industrail Layout,
Koramangala V Block,
Bangalore - 560095
Phone. : 5533622, 5534601, and 5537114
Fax: 5537115

Cranes Software International
NO. 5, Airport Road,
Domlur Layout
Bangalore - 560071
Phone: 5549338
Fax: 5546299

Brainware Infotech
92, Anjaneya, Temple Street,
Bangalore - 560004
Phone. : 6616867, 6616895

8th Floor, Diamond Jubilee Commerecial Complex,
Hudson Circle,
Bangalore - 5600027
Phone. : 2211143
Fax: 2211152

Pertech Computers Ltd.
IV Floor, Shiv Shankar Plaza
19, Lalbagh Road,
Bangalore - 560027
Phone: 91 (80) 2240087, 2273349
Fax: 91 (80) 2273286

PSI Data Systems Ltd.
Shrutta Complex, 19, Primrose Road
Bangalore - 560025
Phone: 91 (80) 5585726
Fax: 91 (80) 5588298
Telex: (0845) 3056 PSIE IN

Mascot Systems pvt. Ltd.
A-208, Block III, Software Technology Park
KSSIDC Complex, Electronics City
Bangalore - 561229
Phone: 8520959, 8520960/1 Fax: 8520958

Digital Equipment (India) Ltd.
(A Subsidiary of Digitial Equipment Corporation, USA)
Digital Park, 92, Industrial Suburb II Stage, Yeshwanthpur
Bangalore - 560022
Phone: 3374785 Fax: 3374601
Telex: (0845) 8758

Repro Press (P) Ltd.
108, Ramanashree Chambers
37, Lady Curzon Road,
Bangalore - 560001
Phone: 91 (80) 5592938, 5598304
Fax: 91 (80) 5592938
Transoft International (P) Ltd.
No. 724, 24th Main Road
VI Phase, J.P.Nagar
Bangalore - 560078
Phone: 6633731

Web sites for jobs and placements:
http://WWW.CNC.CA 80/onlresum.htm

Mail ids of HR

ameetaroy @
asterix @
bagga @
bangalore @
blr_cv @
bnravi @
career @
careers @
careers @;
clblr @
crvcon @
fresh_options @
gr @;
hr_cv @;
hrindia @
hrsearch @
humint @;
india @;
info @;
java @
jdarbar @
jobs @
jobs @
joinus @
kpapola @
krijal @
Linkers @
manojpk @
mktig @
nat @
nrupa @
optimum @
pnvgopali @
rajesh @
rect @
resume @
rpsoft @
teamhr @
tmiblr @
tspahwa @
Want2B @

This is a list of HR persons of various companies in B'lore!

Doc files send to:

1. Dss@Blr.Vsnl.Net.In Datamatics Simi
2. Pegote@Poboxes.Com Pegotei Morgan Sridevi

3. Resume@Blr.Vsnl.Net.In Resource Mgmt
Nikitha 509 7575

4. Jobs@Sampoorna.Com Sampoorna Juliet 529 4330
5. Vista@Bgl.Vsnl.Net.In Vista Cons Sheila
Mathews 2227439/ 5634

6. Tmi.Blr@Smb.Sprintrpg.Ems.Vsnl.Net.In
Tmi Rajani 5292701/8488
7. Abcit@Giasbg01.Vsnl.Net.In Abc Cons
8. Sridhar@Blr.Vsnl.Net.In 6671750/73909
9. Crvcon@Giasbg01.Vsnl.Net.In Crv Cons
10. Alphine@Blr.Vsnl.Net.In Alphine Cons
11. Headhunter.Mas@Rmb.Sprintrpg.Ems.Vsnl.Net.I
n 643894
12. Venugopal.Pnv@Gems.Vsnl.Net.In
P.N.Venugopal Ass. P.N.Venugopal

13. Eurolink@Blr.Vsnl.Net.In Euro Link
14. Hrd@Altair.Soft.Net Altair 2220092
15. Itpeople@Blr.Vsnl.Net.In I.T.People 5597700

16. Btiblr@Blr.Vsnl.Net.In Bti Consulta.
17. Medha@Giasbg01.Vsnl.Net.In Medha Cons
18. Neeraj Jaipuria
19. Lavora Cons Mili
Alex 5542525

20. IT Convergence
Nagendra/Scott 5599955 (9 lines)

22. Ebs Info
23. IT Solutions Mr.Jessy
24. Liaizonei Deepak

26. Nucleus Preethi

27. 6649979-80



30. Personal Network
Prathima 6711318

31. Mind Cons Anil
Kumar 2994030

32. Contact Cons Latha 5281847

33. HRM Cons Madhu 3441369

34. bluestar


36. HP

37. siemens
38. mahindra bti
39. oracle india
Smitha 2256099
48. sap
49. DSQ Software 5593847

50. ALP Career Chithra

51. Ampersand Sunitha 3336173/6388

52. BAEHAL Sandya 5268684/5296678

53. Ellise Software Meera/CS Murali

54. HCL Perot 6680312,86

55. Kshema Technologies 2272933

56. Omam Cons 5252387/5295094

57. Orbit Cons

58. PSI Data Systems 5585726-27

59. Skiline Software 2211961

60. SourceCode Intl
Neeraj 2285452,56

61. Sunitha Global
Vikram 8420500,19,21

62. Tata Infotech 5284681

63. Willys
Placements Mosses 5243990

Text Files Send to:

Without Attachments Send to:

Fresher recruiting companies in Bangalore:

f) SILICON AUTOMATION SYSTEMS ( Electronics Background)
g) MOTOROLA (Electronics Background)