The basic insight was to notice that if you are doing a divide by 3 and wanna keep the duty cycle at 50% you have to use the falling edge of the clock as well.

The trick is how to come up with a minimal design, implementing as little as possible flip-flops, logic and guaranteeing glitch free divided clock.

Most solutions that came in, utilized 4 or 5 flip flops plus a lot more logic than I believe is necessary. The solution, which I believe is minimal requires 3 flops - two working on the rising edge of the clock and generating a count-to-3 counter and an additional flop working on the falling edge of the clock.

A count-to-3 counter can be achieved with 2 flops and a NOR or a NAND gate only, as depicted below. These counters are also very robust and do not have a "stuck state".

The idea now is to use the falling edge of the clock to sample one of the counter bits and generate simply a delayed version of it.

We will then use some more logic (preferably as little as possible) to combine the rising edge bits and falling edge bit in a way that will generate a divide by 3 output (with respect to out incoming clock).

The easiest way (IMHO) to actually solve this, is by drawing the wave forms and simply playing around. Here is what I came up with, which I believe to be *the optimal solution for this approach* - but you are more than welcome to question me!

and here is also the wave form diagram that describes the operation of the circuit, I guess it is self-explanatory.

One more interesting point about this implementation is that it does not require reset! The circuit will wake up in some state and will arrive a steady state operation that will generate a divide by 3 clock on its own.

## 6 comments:

Can you demonstrate how to scale this solution to divide by 5,7,9,.. with 50% duty cycle?

Verified on Spartan 6 s6microboard. Works fine, reliable, no glitches.

I am under the impression that a better implemantation exists and is as follows:

take the 1:3 unit you have designed and out put from the NOR into the clock of a third FF.

Have the input of this FF be the original CLK which we are trying to change. It's output should be 111000111000 ... as requested, for one logic gate less.

I have a pic too but do not have means of sending it.

If you like my comment, I just graduated a week ago from a Computer Engineering degree and am looking for work...

you can contact me at elijeng@gmail.com.

Have a great day:)

On the time-nuts mailing list, this topic came up and a solution with two D FFs and a single XOR gate was presented.

Configure each of the two Ds as a divide-by-two (D fed from !Q). Feed the Q of the first into the clock of the second. So you have a divide-by-four.

The XOR gate is fed from the output of the second flip-flop, which is also the output of the entire circuit, and from the input clock. The output of the XOR is fed into the clock input of the first D.

In the original description, there was a delay line between the second flip-flop's output and the XOR input, but it was noted that this delay is likely optional given the propagation delay of the flip-flops.

I believe the concept is that it's a divide-by-four, but inverting the input when the output changes causes a "stutter count" that quickly skips a step.

sir, please can you explain me with the steps and procedure regarding non-integer frequency divider

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