Thursday, January 31, 2008

Signal integrity approaches meet the multi-Gbps design challenge

start:Signal integrity approaches meet the multi-Gbps design challenge

High-speed data paths now lie on the critical path of product development; you can combine multiple approaches, including S-parameters, for effective signal-integrity analysis

The wireless explosion has spawned a frontier with countless market opportunities for communications companies. The increasing complexity of today's electronics products, however, has created a myriad of issues for designing and bringing to market these technology-rich applications. Electronic design automation (EDA) software is an important tool in the product generation process, and a key concern inherent in the design of next-generation, high-performance communications products is complex cross-domain signal integrity (SI) issues.

Signal integrity (SI) analysis has traditionally been used as a verification step prior to releasing a design for manufacturing. This methodology served the high-speed design community well as clock frequencies and data rates pushed through 100 MHz and approached 1 GHz. But with today's communications designs with data rates of 3 to 5 gigabits/sec (Gbps) and beyond, the fundamental assumptions that used to permit "fixing up" the timing at the end of the design cycle are no longer viable. High-speed data paths now lie on the critical path of product development and a new, more proactive approach to SI is needed.

Multi-Gbps design challenges

The design of high-frequency (above 1 GHz) interconnects can be an issue across all parts of the design, from on the chip itself, moving off the chip and through the packaging, and onto the board, or all of these at the same time. Communications companies who are developing products with increasing frequencies and edge rates, and using traditional printed circuit board (PCB) signal-integrity solutions, are finding that their designs look good in simulation (Figure 1a), but when they build and measure their prototypes they get very different and disappointing results (Figure 1b).

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Figure 1 (a) and (b). Simulated design results (upper image) vs. measured prototype results (lower image).

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Consequently, they find themselves spending excessive time and money on redesigns, re-spins, and experimenting on the test bench, adding cost to their final products not only with additional "fix-it" components (capacitors, inductors, etc.) but ultimately in lost time-to-market opportunities.

Why such large discrepancies between simulated and measured results? At frequencies up to several hundreds of MHz, interconnects can be modeled as lumped, passive-element RLGC or RLCK models. This modeling technique has been effective since the days when SI issues first surfaced starting with 33 MHz PC designs. A single lumped-element equivalent circuit model for interconnects was sufficient to capture high-frequency effects, and allow SI analysis to confirm that timing constraints and signal quality requirements were met.

But at GHz frequencies, with clock edges measured in picoseconds, the old lumped element approximations become grossly inadequate. Interconnects must now be modeled as coupled transmission lines with propagation and loss characteristics having strong frequency dependence due to dispersion, skin effect, and dielectric loss. The result is that the commonly-used RLCK modeling and simulation technology can no longer provide accurate or dependable results. High-frequency models and simulation technology must be incorporated to design, simulate, and validate a manufactured product that will actually work as designed.

Figure 2 displays a spectral analysis of a 1 GHz pseudorandom binary sequence (PRBS) waveform with 100 ps rise/fall edges.

Figure 2. Spectral analysis of a 1-GHz PRBS waveform
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The RLCG models provide enough accuracy up to about 1 GHz, but as this spectrum plot shows, depending upon the system signal-to-noise ratio (SNR), there is significant frequency content from a 1 GHz data rate out to 20 GHz and beyond.

Besides the speed of the signals and edge rates, designing across different manufacturing domains is also a critical issue. In order to optimize system-in-package (SiP) or module designs, it is important to be able to co-design individual die across packaging and sometimes with the PCB. In order to increase confidence in the design, the effects of all components in the signal path should be considered concurrently. A good design system must have the ability to simulate the entire path, including the IC or at least the IC I/O buffers, at the transistor level for the most accurate and dependable results. But most flows today are based on tools that do not permit this kind of seamless interaction between chip and board, and the electrical and physical domains.

Efficient design requires modern data modeling

Traditional EDA tools architectures were developed in the late 1980's and early 90's. The state of the art then was to have a unique database for each step of the design flow and to then integrate databases with layers and layers of software called "frameworks" (Figure 3).

Figure 3. Traditional EDA tools with separate data files for each step vs. modern solutions with a single unified data model.
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The result was that each step of the design process—or "view" of the design—had its own database and its own use-model. This delivers a very serial flow, with any given engineer only able to master one or two steps or tools in the flow. The result is that the design is spread out over many different tools, and it is difficult or impossible to ensure that all the data is synchronized. Synchronization of the design can take hours, days, or weeks, if it happens at all.

More modern solutions have been introduced in the past ten years which offer a completely different approach through a single, unified data model. These include several new technologies that have recently matured: C++ and object-oriented design, and component object modeling and databases. The newer solutions, such as AWR's SI® design suite, which was used in the design methodology for this paper, enable all of the tools or views needed to design GHz electronics to be inherently synchronized by using the same database.

This results in much shorter design cycles, because there is no extra effort needed to synchronize the design. Such an arrangement of single database with multiple tools/views is sometimes referred to as a unifying or unified data model (UDM). With a UDM, there is also no penalty in terms of time or data lost (from incomplete translations) in switching between different steps in the flow.

For the SI analysis flow in flux at multi-Gbps rates, the UDM is a potential solution. Rather than having to wait until very late in the flow to have access to completed layouts for post-layout SI analysis, the UDM provides early incremental access of electromagnetic (EM) simulation results to the SI engineer prior to, or as part of, formal PCB layout. In this way, interconnects for critical serial links can not only be designed before the integrating PCB layout step, they can also be analyzed post-layout, thereby providing a greater degree of certainty that the interconnects will perform adequately at frequency.

Furthermore, the UDM has the ability to concurrently manage multiple stack-ups, or technology files, representing the ICs, their packages, the PCB, and all associated die-to-board electrical models. This gives the SI designer much more flexibility for verification. No longer is it necessary to extract macro-models of IC-level components for simulation with package- and PCB-level models. The SI engineer can now co-design module-level interconnects with driver and receiver circuitry at the transistor level, while including the effects of bond-wires and surface mount PCB devices. Packaging limitations and die constraints can be taken into account early in the design process. This avoids after-the-fact design problems that can result from oversimplified off-die load models, and eliminates the painful debugging process of trying to fix them.

Chip/package/board simulations

In addition to a UDM for concurrency and co-design, powerful simulation technology is needed that can analyze the diverse set of component models comprising signal integrity data links. Figure 4 depicts this need schematically.

Figure 4. Gigabit applications involve modeling a chain of components.
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Transistor-level IC models are needed for accurate I/O buffer and serializer/deserialer (SERDES) phase locked loop (PLL) simulations. Transmission line and S-parameter models are needed for accurate package and interconnect simulations.

One of the very few circuit simulation products addressing this challenge is HSPICE® from Synopsys, Inc. For over 25 years, HSPICE has been the standard in IC circuit simulation. All major foundries provide HSPICE transistor models for sign-off simulation, and chip vendors provide either IBIS or triple-DES encrypted netlists for HSPICE simulation.

The IC-level modeling support of HSPICE is therefore considered the most validated and trustworthy SI solution available. In addition, HSPICE provides two significant technologies for modeling off-chip components: a generalized modeling capability for lossy coupled transmission lines, and the ability to perform simulations directly from S-parameter data sets.

Coupled transmission lines are modeled in HSPICE using an approach based on distributed RLGC matrices referred to as the W-element. The approach is very general and applicable for most interconnect systems, due in part to the ability to represent any number of coupled interconnects, and an ability to handle substantial frequency dependence. Any system of uniform coupled transmission lines can be characterized with RLGC matrices.

Unlike the RLCG models of the past that map to simple lumped-element equivalents, RLGC matrices represent a complete mathematical description of the complex distributed propagation characteristics of coupled transmission line systems. Matrix values can be derived from physical trace geometry, using electromagnetic field solvers (such as HSPICE's built-in 2D EM solver), or by converting from the propagation and impedance parameters used in board-level transmission line component libraries.

Frequency-dependent RLGC matrix values are critical for modeling GHz loss effects due to skin effect (conductors) and loss tangent (dielectrics). Interconnects also possess dispersion at GHz frequencies, resulting in frequency-dependent propagation factors, which are also captured as RLGC frequency dependence. Such methods have allowed W-element models to align with measured data at frequencies as high as 40-110 GHz.

But the most impressive aspect of the W-element is its ability to provide fast and accurate time-domain simulations. Most tools that use frequency-domain models for time-domain simulation employ convolution calculations that are notoriously slow. The W-element, however, uses techniques that efficiently separate propagation, reflection, and loss factors, enabling fast recursive convolution while ensuring causality and passivity.

S-parameters fuel successful SI design

S-parameters, also called scattering parameters, have become the preferred method for characterizing passive components which are not well modeled by SPICE or transmission line methods. S-parameter data sets may originate from EM simulation, from direct vector network analyzer measurements, or from a linear circuit simulation of portions of an SI link. There is a definite trend towards encapsulating much of the off-chip design into a few large S-parameter data sets. In the case of IC package models, very large S-parameter data files may be involved. Efficient handling of such data has therefore become a priority for SI simulation.

The HSPICE S-element allows S-parameter data files to be used directly for simulation. Convolution calculations are performed automatically for time-domain simulation. Several options are available for handling S-parameter data in the most efficient ways possible. For large data files used to represent IC packages, HSPICE generates reduced order models (ROM) that can be efficiently analyzed with recursive convolution.

When S-parameter data is available for transmission lines, the data can be used as input for specifying a W-element model (Figure 5).

Figure 5. HSPICE supports several options for S-parameter data input, including the ability to extract W-element transmission line models from scattering parameter data.
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Transmission-line propagation and RLGC values are then calculated automatically, allowing the W-element to apply fast recursive convolution calculations for time-domain simulation. HSPICE includes a variety of advanced sS-parameter data interpolation and extrapolation schemes to handle things such as proper behavior at DC (zero frequency), insufficient data sampling at resonant frequencies, and smoothing for noisy measurements.

A solution based on a unified data model, combined with the SI simulation strengths of HSPICE, offers unique design flow advantages to meet the needs for multi-Gbps SI design and simulation. The design software adaptively maps complete chip/package/board links into simulation-ready HSPICE models. For distributed elements, models can be mapped from a passive element library validated for microwave applications, up to and beyond 100 GHz, into the HSPICE W-element for single schematic co-simulation in frequency- and time-domains.

The HSPICE software also includes a special interface layer for rational function approximations of S-parameter data sets. Using Foster's canonical form, the interface enforces passivity and guarantees causality for HSPICE time-domain simulation, whether directly from S-parameter data files or the result of integrated, concurrent EM analyses within the design suite. This, combined with HSPICE's trustworthy IC device and IBIS models, provides a comprehensive chip/package/board signal integrity simulation solution. High data-rate signal paths can be designed with on-chip and off-chip awareness, and then taken to fabrication by exporting to enterprise PCB tools.


The design of next-generation, high-performance communications products requires the consideration of complex cross-domain SI issues. This paper has outlined a modern SI design methodology that utilizes a top-down approach to IC, packaging, and PCB SI, enabling engineers to meet the challenges presented by multi-Gbps design issues. This approach solves many SI issues early in the design phase, prior to analysis, saving design iterations and shortening time-to-manufacture.

About the authors
Scott Wedge, Ph.D ( is a senior staff engineer with Synopsys Corporation. He has authored numerous technical papers on RF/microwave theory and design, is a former Howard Hughes Doctoral Fellow, and holds two patents in RF/microwave technology.

Mike Heimlich, Ph.D ( is the microwave market segment director for Applied Wave Research, Inc. He has published papers in many technical journals and proceedings on MMIC and module design and EDA tool integration, and holds a patent in EDA tool integration.

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