Thursday, January 3, 2008

Thoughts of VLSI Design Engineer

Lets now try to study the mind of an Good RTL designer

As soon as the Designer has a specification to write an RTL. He studies his neighbours(his nearby modules ) to know who gives him data and to who he has to deliver the data.
so his first work is to prepare the stub file(skeleton of ports list). say the clock names,reset signals, input and output signals, scan signals…
Now he has the stub file ready he can pass it on to the placement person(if he is interested in preparing the floorplan).
Now his next thought is to prepare a micro-architecture of the specification, study the electrical specifcation and prepare the timing-diagrams required of his module. As well he needs to think of internal partitioning of the blocks to minimize the complexity involved and to concentrate well.
Study on Bus-Architectures which are the performance booster's
http://www.vlsichipdesign.com/busarchitectures.html
Now the Designer has studied his specification well now internally in his mind he discusses about the various trade-off's like
* Memory or a Register Files (pro's and Con's).
* Synchronous reset or Asynchronous Resets.
* How to ensure that the DFT(Design for Test) related clocks to reach all the flops.
http://www.vlsichipdesign.com/test.html
* In case of any cross-clocking or in case if his design has multi-clocking structures need to better understand the data transfer mechanism , like hand-shaking, FIFO requirements, depth of FIFO, synchronizers and all to prevent Metastability and ensure proper data transfer.
http://www.vlsichipdesign.com/FIFO_depth.html
* Understanding of Good Coding Styles
http://www.vlsichipdesign.com/verilog_coding_styles.html
* Understanding of Timing Requirements in the design (Scenario's where Falsepath's/Multicycle-paths ).
To understand how to achieve faster timing closure
http://www.vlsichipdesign.com/timing_closure.html
To understand the concepts of Static Timing Analysis
http://www.vlsichipdesign.com/static%20timing%20analysis.html
To understand what all to think while preparing the Design timing constraints
http://www.vlsichipdesign.com/synopsys_constraints.html
* Understand the depth of the combinational logic between sequential: This could be an issue for meeting timing requirements if the logic levels are more and increase in the test-pattern generation in the DFT.
* how to write an RTL how generic it could be.
* How to write RTL so that it could be power friendly like have module enable signal's, and enable signal generation logic so that automatic clock-gating insertion is friendly
http://www.vlsichipdesign.com/clockondemand.html
* How to write an RTL so that it is friendly for Verification(say Assertion based tools to generate on Assertions).
To understand the various Verification Methodologies
http://www.vlsichipdesign.com/asic_verification.html
* Writing Synthesis Friendly RTL Coding.(say for example the code synthesis to a priority-encoder for a requirement of a MUX, the code comes with a latch in case if all the possible states are not defined in a switch-case statement or else mentioning with a default switch and things like that).
* Writing RTL power optimized. in case if the requirement is for using DVFS(Dynamic Voltage Frequency scaling) then preserving the states of the control register's(Decision makers of the design) with a State retention based flops some thought ahh..
To know the various Sources of power dissipation in an CMOS design
http://www.vlsichipdesign.com/power_in_CMOS.html
these are the few thoughts….

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