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VLSI Design Verification
For Sharing ASIC/FPGA Design Verification Experiences
Sunday, April 24, 2016
SV constraint example
Constraint c_valid_rate;
constraint
phyFrameRandFullSeq::c_valid_rate {
Solve
mPktType
before
mBaseRate;
if
(mPktType == WIFIDOT) {
mBaseRate
inside
{1, 2, 5, 11};
}
else if
(mPktType == WIFIDOT1) {
mBaseRate inside { 6,12, 18} ;
}
}
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Signal Integrity
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