System Verilog Questions

 1. When enumerated data types are used? 

  Requirement for variable that can only take on fixed set of data value Ex: traffic_light takes red, green, yellow

typedef enum bit [1:0] { red, yellow, green} light_e;

light_e v1,v2;

  Enums have strong type checking 

  Ex: v1 = blue; // will generate error

Methods to handle enum types:

first(), last() , next(int n), prev(int n)

Why data structures are used? 

-> More efficient to build and maintain models 

-> Less error prone 

ex: 

typedef struct {

 bit [15:0] source_addr;

bit [15:0] dest_addr;

bit [63:0] patload;

} my_pkt_struct;

my_packet_struct s;

s.dest_addr[];

2 types of stuctures 

-> Packed

-> Unpacked

typedef struct packed signed { 

    bit [63:0] payload;

   logic [31:0] dest_addr } my_pkt;

Bit slicing, arithmetic & logic operations are supported. 

Ex: byte [9:0] sram; // packed 

Unpacked (Default): 

Bit slicing on unpacked struct is illegal 

Ex: bit sram [7:0][9:0]; 

       int u [7:0] 

String Data type:  String is dynamic array of characters 

Dynamic Array: Unpacked

 int mem_data[];

bit [7:0] crc[];

big_pict[][];

   Methods: 

  new : Allocates storage during runtime 

  size : returns current size of dynamic array 

 delete : removes all elements of the array 

Ex: // declaration 

      bit [7:0] d_array1[];

   // memory allocation 

     d_array1 = new[4];  // 4 elements 

 // to allocate 6 new elements & retain values of 4 elements 

   d_array1= new[10](d_array1); 

// delete 

  d_array1.delete;

Tasks & functions: 

-> To describe subroutines 

-> Provide the ability to execute common code used repeatedly in the design

-> Breakup large procedures into similar manageable units 

-> Easy to read 

Tasks	Functions
Can have time controlling statements	Can't have time controlling statemens ( all statements in the body execute in 1 sim time unit)
Can enable other tasks & functions	Can't enable other tasks
Can't return a value through task name ( values passed only though input/output arguments	Can return one value through function name
default data type is logic and default direction is input

Passing Arguments by Reference: 

-> Avoids large data copies 

-> Better simulation performance 

Static	Automatic
Default mode when declared within a program/module/interface/package	Default mode when declared within a class
All declared items are statically allocated	All declared items are dynamically allocated
Specific items can be declared automatic using keyword "automatic"	Specific items can be declared automatic using keyword "static"
Items can be accessed using hirarchical names

 

Shallow copy: Only first level of properties are copied using the shallow copy. not the objecs inside the parent class 

Ex:  

A1 = new();

A2 = new A1; 

Deep copy: 

L1 = new();

L2 = new();

L2.copy(L1); 

ref: https://verificationguide.com