VLSI Design Verification

Using model-based design in signal integrity engineering By Colin Warwick, The MathWorks RF techniques, originally developed for wireless communication projects, are being repurposed to solve the increasingly complex problem of preserving signal integrity in high-speed data transmission between chips joined by backplanes and printed circuit boards. These pin-to-pin connections are becoming mini-communication systems in their own right. In parallel, Model-Based Design is being adopted for these projects to significantly speed the design process, through a graphical environment with prebuilt, optimized algorithms and blocks. This article addresses the convergence of these two trends. Planning a typical application We'll use Model-Based Design and RF techniques to create an impairment model of the backplane that is used as a test environment in both the modeling and design phases for the development of mitigating algorithms. The first step is to ...

start:Signal integrity approaches meet the multi-Gbps design challenge High-speed data paths now lie on the critical path of product development; you can combine multiple approaches, including S-parameters, for effective signal-integrity analysis By Dr. Mike Heimlich, Applied Wave Research, Inc. and Dr. Scott Wedge, Synopsys, Inc. The wireless explosion has spawned a frontier with countless market opportunities for communications companies. The increasing complexity of today's electronics products, however, has created a myriad of issues for designing and bringing to market these technology-rich applications. Electronic design automation (EDA) software is an important tool in the product generation process, and a key concern inherent in the design of next-generation, high-performance communications products is complex cross-domain signal integrity (SI) issues. Signal integrity (SI) analysis has traditionally been used as a verification step p...

FPGA-Based Prototyping - "Productivity to Burn" This article highlights recent tool advances that can help you setup, implement, and verify your FPGA-based ASIC prototype faster than ever before. By Lee Hansen (Xilinx) and Doug Amos (Synplicity) Programmable Logic DesignLine (01/30/2008 2:02 PM EST) These days, a large portion of ASIC, SoC, and ASSP designs are at least partially prototyped in one or more FPGAs. This amounts to many thousands of prototyping projects per year. Compared with other ASIC verification methods, however, FPGA Prototyping is mistakenly seen by many as an ad-hoc mix of tools that must be cobbled together by hand. In reality, powerful integrated tools, platforms, and expertise exist that greatly improve the productivity of FPGA-based ASIC prototyping. This article highlights recent tool advances that can help...

Tackle team-based FPGA design You see them at almost every user seminar or industry trade show workshop: the Methodology Managers from XYZ Corporation, who describe the system they use to help the company make sense of the intellectual property (IP) produced by their design teams. And it's got to be a daunting task--development staff working in different time zones; language barriers; software tool versions to track and synchronize; VHDL/Verilog/C/C++, CAD databases. All of these (and more) diminish the reusability of any design module. You can respect the role these managers play and envy the sanity they bring to the organization. But XYZ Corporation is a large company. How does a small or midsize firm like yours grapple with this imposing housekeeping chore? Distributed design teams happen. With the right mix of specialty tools and culture, it's becoming more practical to create and manage distributed FPGA design teams by using modular FPGA design methods that allow multiple ...

The basic insight was to notice that if you are doing a divide by 3 and wanna keep the duty cycle at 50% you have to use the falling edge of the clock as well. The trick is how to come up with a minimal design, implementing as little as possible flip-flops, logic and guaranteeing glitch free divided clock. Most solutions that came in, utilized 4 or 5 flip flops plus a lot more logic than I believe is necessary. The solution, which I believe is minimal requires 3 flops - two working on the rising edge of the clock and generating a count-to-3 counter and an additional flop working on the falling edge of the clock. A count-to-3 counter can be achieved with 2 flops and a NOR or a NAND gate only, as depicted below. These counters are also very robust and do not have a "stuck state". The idea now is to use the falling edge of the clock to sample one of the counter bits and generate simply a delayed version of it. We will then use some more logic (preferably as little as possible) ...

List of Company Addresses X-Vision Software 945, 24th Main IInd Phase, J.P.Nagar Bangalore - 560 078 Phone: 646634 Worldscope Disclosure India Pvt. Ltd. 106, First Floor, Gandhi Bazaar Road Basavanagudi Bangalore - 560004 Wishbone Systems Pvt. Ltd. 968, 12th Main Road HAL II Stage Bangalore - 560 008 Phone: 5276717 Fax: 5276717 Wipro Systems Ltd. 3rd Floor, S.B.Towers No.88, M.G.Road Bangalore - 560 001 Phone: 5586202, 5588583 Fax: 5587984 Wipro InfoTech Group 88 MG Road, Bangalore - 560001 Phone: 5588422 Fax: 5586657 Wipro GE Medical Systems Plot No. 4, Kadugodi Indl. Area Sadaramangala Bangalore - 560057 Phone: 8452923/25/26 Visual Engineering Services (I) Ltd. A-313, Block III, KSSIDC Multi Storied Complex Keonics Electronics City, Hosur Road Bangalore - 561229 Verifone India Pvt. Ltd. Indian Express Building Dr. Ambedkar Road Bangalore - 560 001 Phone: 2269920, 2269924 Fax: 229938 Unitech Systems (India) Pvt. Ltd. III Floor, Classic Court 9/1, Richmond Road Bangalore - 560 025 Phon...