SoC/IP level test plan
1. CSR tests
POR, Read/Write, aliasing, Walking ones, walking zeros
2. Bring up
Program/configure. Send commands
3. Varies interface tests
4. Power management tests
5.Error conditions
6. Concurrent cases tests
7. Reset scenarios
SVA for Timing checks
Write assertion to check delay from posedge clk to any change on signal "meta" must be less than 300ps.
property p_max_time(start, stop, duration);
time start_time;
@(start)
(1, start_time = $time) |=>
@(stop)
( ($time - start_time <= duration);
endproperty
a_meta_sub_cycle: assert property(p_max_time(posedge clock, meta, 300ps));
Interview Questions
@DI Interview Questions:
1. Difference between components and objects?
2. Why do components have hierarchy?
3. Sequencer and driver communication?
4. Sequence and sequencer communication?
5. How sequencer and sequence are connected?
6. what is m_sequencer?
7. Difference between copy() and clone() and advantages of copy and clone?
8. Advantages of uvm macros like `uvm_field_int?
9. What is clocking block and mod port?
10. Why do we need mod port if we can specify direction in clockig block?
11. what is port, export and implementation port? Difference between export and implementation port?
12. Let us say a dynamic aray is having size 5. Each location is of 1bit size. Write a constraint so that every time when we randomize three locations should be 1 and two locations should be 0?
13. Inheritance:
Claas A;
endclass
Class B extends class A;
int ab;
endclass
A a0;
B b0,b1;
->a0 = b0 is it possible?
->Can we access a0.ab?if not why? What will happen to ab property?
->$cast(b1,a0) is it possible?
->Can we access b1.ab?
->How we can access b1.ab if we were not able to access it using a0 handle?
14. What is virtual class? and Advantages?
15. Scripting experience.
16. A memory with 99 elements. The value in each location is repeated except one location. How you will find it?
17. logic for the below scenario:
input array [`Parameter:0]a;
dynamic array A,B;
logic:
A[0]=a[7:0];
B[0]=a[15:0];
A[1]=a[23:16];
A[2]=a[31:24]; so on..
sv constraint with number of bits 1
a)Write constraints so that myvec1 has atleast 10 but no more than 18 bits set as 1
b) Also, myvec2 has more than 5 bits that are set to 1 but number of bits that are 1 should be lesser than the number of bits that are 1 in myvec1
rand bit [31:0] myvec1;
rand bit myvec2[32];
constraint c_myvec1 {$countones(myvec1) >9;$countones(myvec1) <18;}
constraint c_myvec2 { int’(myvec2.sum) >5;
int’(myvec2.sum) < $countones(myvec1) } ;
System Verilog Questions
1. When enumerated data types are used?
Requirement for variable that can only take on fixed set of data value Ex: traffic_light takes red, green, yellow
typedef enum bit [1:0] { red, yellow, green} light_e;
light_e v1,v2;
Enums have strong type checking
Ex: v1 = blue; // will generate error
Methods to handle enum types:
first(), last() , next(int n), prev(int n)
Why data structures are used?
-> More efficient to build and maintain models
-> Less error prone
ex:
typedef struct {
bit [15:0] source_addr;
bit [15:0] dest_addr;
bit [63:0] patload;
} my_pkt_struct;
my_packet_struct s;
s.dest_addr[];
2 types of stuctures
-> Packed
-> Unpacked
typedef struct packed signed {
bit [63:0] payload;
logic [31:0] dest_addr } my_pkt;
Bit slicing, arithmetic & logic operations are supported.
Ex: byte [9:0] sram; // packed
Unpacked (Default):
Bit slicing on unpacked struct is illegal
Ex: bit sram [7:0][9:0];
int u [7:0]
String Data type: String is dynamic array of characters
Dynamic Array: Unpacked
int mem_data[];
bit [7:0] crc[];
big_pict[][];
Methods:
new : Allocates storage during runtime
size : returns current size of dynamic array
delete : removes all elements of the array
Ex: // declaration
bit [7:0] d_array1[];
// memory allocation
d_array1 = new[4]; // 4 elements
// to allocate 6 new elements & retain values of 4 elements
d_array1= new[10](d_array1);
// delete
d_array1.delete;
Tasks & functions:
-> To describe subroutines
-> Provide the ability to execute common code used repeatedly in the design
-> Breakup large procedures into similar manageable units
-> Easy to read
| Tasks | Functions |
| Can have time controlling statements | Can't have time controlling statemens ( all statements in the body execute in 1 sim time unit) |
| Can enable other tasks & functions | Can't enable other tasks |
| Can't return a value through task name ( values passed only though input/output arguments | Can return one value through function name |
| default data type is logic and default direction is input | |
Passing Arguments by Reference:
-> Avoids large data copies
-> Better simulation performance
| Static | Automatic |
| Default mode when declared within a program/module/interface/package | Default mode when declared within a class |
| All declared items are statically allocated | All declared items are dynamically allocated |
| Specific items can be declared automatic using keyword "automatic" | Specific items can be declared automatic using keyword "static" |
| Items can be accessed using hirarchical names | |
Shallow copy: Only first level of properties are copied using the shallow copy. not the objecs inside the parent class
Ex:
A1 = new();
A2 = new A1;
Deep copy:
L1 = new();
L2 = new();
L2.copy(L1);
ref: https://verificationguide.com
AHB assertions
property ahb_incr16_htrans_p; @(posedge clk) disable iff ( HTRANS == BUSY || HBURST != INCR16) (HTRANS == NONSEQ) |=> (HTRANS |=> SEQ ) |=> (HTRANS == SEQ)[*14] endproperty
property ahb_incr4_htrans_p; @(posedge clk) disable iff ( HTRANS == BUSY || HBURST != INCR4) (HTRANS == NONSEQ) |=> (HTRANS |=> SEQ ) |=> (HTRANS == SEQ)[*2] endproperty
// To check AHB incrementing bursts crossing 1KB boundary property ahb_1kb_boundary_p; @(posedge clk) disable iff (~rst_n) (HTRANS == SEQ) |=> (HADDR[10:0] != 11'h400); endproperty
// To check AHB incrementing address during incrementing bursts property ahb_incr_addr_p; @(posedge clk) disable iff (~rst_n) (HTRANS == SEQ) && (HBURST inside {INCR, INCR4, INCR8, INCR16}) && ($past(HTRANS,1) !=1)
&& ($past(HREADY, 1)) |-> (HADDR == ($past(HADDR, 1) + 2**HSIZE)); endproperty
// To check AHB OKEY for IDLE transfers property ahb_idle_okey_p; @(posedge clk) disable iff (~rst_n) (HTRANS == IDLE) && (HRESP == OKEY) |=> (HRESP == OKEY); endproperty
// To check AHB 2cycle ERROR response property ahb_error_response_p; @(posedge clk) disable iff (~rst_n) $fell(HREADY) && (HRESP == ERROR) |=> (HRESP == ERROR) endproperty
// To check stable HADDR HWRITE HWDATA until HREADY property ahb_htrans_wait_for_hready_p(HTRANS, HREADY); @(posedge clk) (!HREADY) |=> $stable(HADDR && HWRITE && HWDATA ); endproperty
// To check stable HTRANS until HREADY property ahb_htrans_wait_for_hready_p(HTRANS, HREADY); @(posedge clk) HTRANS inside { NONSEQ, SEQ} && !HREADY |=> $stable(HTRANS) throughout HREADY [->1]; endproperty
Interview questions
event.trigger vs event.triggered
uvm event vs global event
array element constraint for ascending order
deep copy , show copy ex
soft
for {
fork
automatic variable
join
parent class
settype override
object override
how to know randomize() done or not? no constraint then?
callback vs virtual methods
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