VLSI Design Verification

VLSI Design Verification

RTL · Simulation · Formal

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August 07, 2020

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About

Jagadish: I’m Jagadish, a Senior Engineer specializing in SoC/IP verification and emulation, currently focused on CDMA IP verification. Over the past decade, I’ve worked with leading technology companies including Qualcomm, Microsoft, Goodix Technology, and NXP, contributing to complex silicon programs and system-level verification flows. My expertise spans AXI, DMA, LPDDR memory controllers, and UVM-based verification, with a deep understanding of timing, buffer management, and debug methodologies. I’m passionate about making advanced verification concepts accessible — whether through technical writing, workshops, or hands-on demos. Beyond engineering, I design STEM workshops that blend robotics, AI, and playful learning for students. My goal is to inspire curiosity and help young minds connect theory with real-world technology.

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Categories

Digital Design
Formal Verification
Protocol
System Verilog

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VLSI Design Verification — RTL · Simulation · Formal Methods