Git commands

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git log
git branch 
Git pull —rebase
Git diff 

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Design a clock divide-by-3 circuit with 50% duty cycle

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The basic insight was to notice that if you are doing a divide by 3 and wanna keep the duty cycle at 50% you have to use the falling edge of the clock as well. The trick is how to come up with a minimal design, implementing as little as possible flip-flops, logic and guaranteeing glitch free divided clock. Most solutions that came in, utilized 4 or 5 flip flops plus a lot more logic than I believe is necessary. The solution, which I believe is minimal requires 3 flops - two working on the rising edge of the clock and generating a count-to-3 counter and an additional flop working on the falling edge of the clock. A count-to-3 counter can be achieved with 2 flops and a NOR or a NAND gate only, as depicted below. These counters are also very robust and do not have a "stuck state". The idea now is to use the falling edge of the clock to sample one of the counter bits and generate simply a delayed version of it. We will then use some more logic (preferably as little as possible) ...
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Memory power reduction

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 *  Memory retention voltage depends on PVT   * Leakage during memory state retention ( Data retention during standby)  * As retention time increases more errors    Solutions:  1. Voltage scaling ( as VDD reduces number of errors increases , Leakage current )  2. Error correction codes  Effect of ECC:  1. max 1 error per line can be corrected, 2 errors can be detected  2. Area: Memory size increase by (n-k)/n    small additional area for encoder and decoder units ( Fully combinational blocks)  3. Latency : Encoding latency added to write access                      Decoding latency added to read access  For SEC/SED  Number of data bits    No of check bits 8-11                                  5 12-26                 ...
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SVA

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SystemVerilog Assertions: A Comprehensive Guide SystemVerilog Assertions: A Comprehensive Guide In the world of hardware design, simply creating a circuit isn't enough. You also have to prove that it works exactly as intended. One of the most powerful ways to do this is through formal verification , and a key component of that is using SystemVerilog Assertions (SVAs) . SVAs are properties, or statements, that define the expected behavior of your design. They act as a formal specification, allowing tools to mathematically check for correctness. The industry standard for these properties is defined by IEEE 1800-2017 . The Three Basic Types of SVA Statements There are three fundamental types of statements you can use in SVA to define the correctness of your design: Assertions: These are statements about your design's behavior that should always be true . For example, you might assert that a bus protocol's hand...
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