VLSI Design Verification

Callback is a method that is executed every time a known event occurs  Testbench notification Access occurs to the memory Packet/Transaction is processed No polling required Example uses of Callbacks End to end checking of data from testbench to DUT to testbench Error injection Check for spurious or unnecessary transactions Collect functional coverage statistics 

The goal of verification is complete testing the design according to specification with the highest quality in the shortest period of time. Environment creation and testcase development Coverage Finding bugs in early stage Mixedsignal, Clock and reset GLS

FC is watchdog and extra check   Checks both Design and its Verification Qualities  helps develop new testcases for verification completeness  To implement Functional Coverage we need to understand Design Spec 

Constraint c_valid_rate; constraint phyFrameRandFullSeq::c_valid_rate {     Solve mPktType before mBaseRate; if  (mPktType == WIFIDOT) {  mBaseRate inside {1, 2, 5, 11}; } else if (mPktType == WIFIDOT1) { mBaseRate inside { 6,12, 18} ;   } }