System Verilog Questions
1. When enumerated data types are used? Requirement for variable that can only take on fixed set of data value Ex: traffic_light takes red, green, yellow typedef enum bit [1:0] { red, yellow, green} light_e; light_e v1,v2; Enums have strong type checking Ex: v1 = blue; // will generate error Methods to handle enum types: first(), last() , next(int n), prev(int n) Why data structures are used? -> More efficient to build and maintain models -> Less error prone ex: typedef struct { bit [15:0] source_addr; bit [15:0] dest_addr; bit [63:0] patload; } my_pkt_struct; my_packet_struct s; s.dest_addr[]; 2 types of stuctures -> Packed -> Unpacked typedef struct packed signed { bit [63:0] payload; logic [31:0] dest_addr } my_pkt; Bit slicing, arithmetic & logic operations are supported. Ex: byte [9:0] sram; // packed Unpacked (Default): Bit slicing on unpac...