VLSI Design Verification

  square matrix of size odd number and no duplicate max element in rows. | Verification Academy

 1. CSR tests   POR, Read/Write, aliasing, Walking ones, walking zeros  2. Bring up    Program/configure. Send commands 3. Varies interface tests 4. Power management tests  5.Error conditions  6. Concurrent cases tests 7. Reset scenarios 

 Write assertion to check delay from posedge clk to any change on signal "meta" must be less than 300ps.  property p_max_time(start, stop, duration);       time start_time;    @(start)     (1, start_time = $time) |=>   @(stop)  ( ($time - start_time <= duration); endproperty  a_meta_sub_cycle: assert property(p_max_time(posedge clock, meta, 300ps));

  @DI Interview Questions: 1. Difference between components and objects? 2. Why do components have hierarchy? 3. Sequencer and driver communication? 4. Sequence and sequencer communication? 5. How sequencer and sequence are connected? 6. what is m_sequencer? 7. Difference between copy() and clone() and advantages of copy and clone? 8. Advantages of uvm macros like `uvm_field_int? 9. What is clocking block and mod port? 10. Why do we need mod port if we can specify direction in clockig block? 11. what is port, export and implementation port? Difference between export and implementation port? 12. Let us say a dynamic aray is having size 5. Each location is of 1bit size. Write a constraint so that every time when we randomize three locations should be 1 and two locations should be 0? 13. Inheritance: Claas A; endclass Class B extends class A; int ab; endclass A a0; B b0,b1;       ->a0 = b0 is it possible? ->Can we access a0.ab?if not why? What will happen to ab pr...

Assertions:

  https://www.edaplayground.com/x/SR7f

 a)Write constraints so that myvec1 has atleast 10 but no more than 18 bits set as 1     b) Also, myvec2 has more than 5 bits that are set to 1 but number of bits that are 1 should be lesser than the number of bits that are 1 in myvec1  rand bit [31:0] myvec1; rand bit myvec2[32]; constraint c_myvec1 {$countones(myvec1) >9;$countones(myvec1) <18;} constraint c_myvec2 {           int’(myvec2.sum) >5;                                                                        int’(myvec2.sum) < $countones(myvec1) } ;

 Please check the below code  https://www.edaplayground.com/x/cfv_