VLSI Design Verification

  Que vs Ass array  grep 10 errors across multiple files  string swap -> char *c, type casting?  constraint order  vip integration  uvm wrapper  innterface  clocking block git branch, merge, clone  leadership  ssn genration linked list inn SV  singleton class , can be instantiated once.. reporting phase?  busmatrix with input ports , output ports 

  Approach Computational Element Cycles per Sec (100M gates) Vendors S/W Simulations X86 Cores under 1 Cadence Xcelium, Synopsys VCS, Mentor Questa Simulation acceleration GPU processing elements 10 to 1000 Rocketick Processor Based emulation Custom processors 100k to few M Cadence Palladium FPGA Based Emulation FPGA gates 500k to few M Mentor Veloce, Synopsys ZeBu FPGA Prototyping FPGA gates 500k to 50M S2C, Cadence Protium, Synopsys HAPS Market Trends :  Chip Complexity  SoC Focus Software Content  System Integration Typical SoC Simulation Vs Emulation Simulations are becomes slow as design size increases  Emulation/Accelaration can run in terms of Mhz  Best Choice ? depends Performance vs Ease of use/Flexibility/Debug  S/W validation Palladium Platform VXE : verification Xccelarator ...