VLSI Design Verification

 *  Memory retention voltage depends on PVT   * Leakage during memory state retention ( Data retention during standby)  * As retention time increases more errors    Solutions:  1. Voltage scaling ( as VDD reduces number of errors increases , Leakage current )  2. Error correction codes  Effect of ECC:  1. max 1 error per line can be corrected, 2 errors can be detected  2. Area: Memory size increase by (n-k)/n    small additional area for encoder and decoder units ( Fully combinational blocks)  3. Latency : Encoding latency added to write access                      Decoding latency added to read access  For SEC/SED  Number of data bits    No of check bits 8-11                                  5 12-26                 ...

 Introduction:  Improve quality & reuse waste by avoiding:  -> Missing/incorrect product capability (required customer functionality not supported) -> Rework cost ( redesigns & unplanned tape outs) -> Customer quality issues ( customer validation failures, field returns) Requirements Management must provide effective and efficient:  -> Specification of product requirements to meet customer needs -> Implementation of the required functionality according to produce specification  -> Verification & Validation to confirm design & implementation compliance to produce specification  MRD ( Market Requirement Document PRD Product Requirement Document  RS  Product Requirement Specification AS  IP RS IP AS  Design