Introduction to SystemVerilog Clocking Blocks
How do I use SystemVerilog clocking blocks in VCS? What are the delays between the Design Under Test and the testbench? Answer: Clocking blocks are used to ensure that a Testbench (TB), in a program block, communicates synchronously with the Design Under Test (DUT). The TB and DUT should be connected with an interface, and the clocking block should be put into the interface. Start with a simple D-flip flop with a d input and q output (both synchronous). It uses the following interface: interface dff_if (input bit clk); logic q, d; clocking cb @(posedge clk); input q; // TB input output d; // TB output endclocking modport DUT (input clk, // Design under test input d, output q); modport TB (clocking cb); // Synch signals endinterface: dff_if This has two modports, one for the DUT (the dff) and one for the TB. The clocking block is only used by the TB. How does the testbench drive ...