Monday, February 18, 2008

Terminalogy

Antenna Effect: During the processing of VLSI chips,the wafers can
collect charges.If a long metal line is getting connected to a gate
(which typically will be) ,and if this strip of metal collects
enough charges to breakdown the gate,the gate gets damaged
permanently. TO avoid this people use various techniques like going
to one metal above and coming back if they think that the metal strip
is very long.Other technique is to have a diode connected to the
metal line in a proper direction to discharge these extra charges.

Electromigration: As the name suggests,when very large currents flow
in a metal and if the metal is not able to carry that much current,
it(the metal strip) may get knocked out creating a open here,and
short somewhere else(plausible).Basically the metal width and
thickness should be sufficient to carry that much current.This is a
reliability issue.It can happen at any "micron" technology,not only
sub-micron.

Cross-talk: This term is interchangeably used with coupling
capacitance. It is self-explanatory.

The reason for antenna effect is still debated.Whatever the reson is
like the metal line connected to a gate getting charged or
someother,if the metal line length to gate area is more than some
critical value,it is seen that gate gets damaged.So people tend to
limit the length of the metal line.

Are you considering the issue of cross-talk. Cross-talk is related to
line length and proximity of two lines. Thus, long adjacent lines can
couple better than short lines. Is this what you consider? Or, are
you purposely limiting the length of the line because of some other
manufacturing issue. Why impose a rule unless you understand the
reason?

Crosstalk is dynamic problem,ie when the device is in operation,it is
a speed issue,not a reliability issue.But,the thing being talked
about here is a reliability issue and it is related to the process.
The above section talks about the charges that would build up on the
metal interconnects during high energy plasma processes such as dry
etching in fabrication. These charges may eventually end up at and
cause damage to the thin gate oxide of the transistors. The charge
build up is understood to be due to plasma non-uniformity in the
reactors. The effect can be partly be prevented by maintaining
uniform plasma in the reactor as well as by providing on-chip
protection elements such as clamp diodes across thin gate oxides.
Design rules that take into account the antenna ratios i.e., for a
given gate oxide area, the maximum interconnect length and area that
can be supported before a protection diode is needed are usually
followed.

Antenna efects are are long floating interconnects that acts as
temporary capacitors during the metalisation process.Because a
conducting path to ground does not exist at the time of metalisation,
a random discharge from the floating nodes can cause permanent gate
oxide damage. Since it is a mater of capacitance, length and other
dimensions of the interconnect also plays a role. Solution: Inserting
buffers or diodes near the input pins to provide conducting path to
ground eleminates this problem And there is a way to minimize the no.
of charges collected by floating node by inserting jumpers.

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