**Planning a typical application**

We'll use Model-Based Design and RF techniques to create an impairment model of the backplane that is used as a test environment in both the modeling and design phases for the development of mitigating algorithms.

The first step is to use a vector network analyzer (VNA) to measure the frequency-domain response of the backplane and record it in an S4P (four-port) Touchstone file. Modified rational functions are then used to fit the frequency domain data to a time-domain behavioral transfer function. The resulting transfer function is used as a test environment in the development of mitigating algorithms in a Simulink® model. A Verilog-A version of the transfer function is generated for verification of the circuit design. The circuit design can be based on the model and completed using electronic design automation (EDA) tools.

**Signal integrity challenges**

The increasing speeds used in telecommunication and data communication infrastructures have made it more difficult than ever to achieve data transmission at sufficiently low bit error rates (BERs). A signal sent from a gigabit per second transmitter on the I/O pin of one chip travels first along a trace on a plug-in card, then across a backplane to another plug-in card that contains the receiving chip. The signal often becomes degraded by intersymbol interference (ISI), frequency-selective attenuation, and crosstalk. The ISI impairment is caused by reflections, typically caused in turn by impedance mismatch at various interconnection discontinuities. These impairments become more severe as the data rate increases. By contrast, when data rates are below 1 Gb/s, we can rely on a fairly flat backplane frequency response. Also, the echoes of previous pulses decay before the next one comes along, so ISI is less of an issue.

Today, data rates are usually well above 1 Gb/s, so the echo decay time is longer than the pulse spacing, and the received pulse is mixed up with echoes of the previous pulse. The job of signal integrity engineering is to mitigate this and other impairments. Design of adequate mitigating algorithms, such as a pre-emphasis filter for the transmitter and a decision feedback equalizer (DFE) for the receiver, requires an accurate model of the impairment.

The fact that the backplanes and the chips with the I/O transceivers are produced by different companies increases the complexity of the design process. In order to facilitate a dialog between these two groups, equipment manufacturers develop behavioral models of the backplane. Semiconductor companies use these models as a test environment for transceiver design. Chip companies furnish behavioral models of the I/O design so that backplane makers can check the range of backplane designs in which the transceiver can operate successfully. The design process naturally involves a fair amount of iteration because when the equipment manufacturer changes a design it may change the test environment for the chip maker and vice versa. The companies involved typically go back and forth modifying their designs and models until the complete system meets performance specifications.

**Applying the modified rational function method**

We can simplify the design process for the data transmission application using Model-Based Design. The transmission line will be modeled as a modified rational function using MATLAB and RF Toolbox . A modified rational function is a transfer function in the form of a particular type of Laplace transform. The general Laplace transform is the integral over time of a function of time

*f(t)*with a complex sine wave

*e*

^{-st}

In the modified rational function, f(s) consists of residues *c _{j}*and poles

*a*which are complex conjugate pairs. Correspondingly in the time domain,

_{j}*f(t)*consists of a direct feed term

*dδ(t-t*plus a set of exponentially decaying sine waves, which begin after the principle delay t

_{d})_{d}

The modified rational function has the following advantages:

- We can achieve the same level of accuracy as the IFFT method, with a model that is one or two orders of magnitude simpler.
- Model order reduction can be used to trade off complexity and accuracy through the use of fitting parameters.
- Typical VNA data has a low frequency cutoff at around 20 to 50 MHz, so an extrapolation to DC is needed. With IFFT models, there is nothing to prevent the extrapolated phase from being nonzero, which corresponds to a nonphysical delay.
- This can be avoided by writing a constraint algorithm, but this takes time. In contrast, rational models represent a physical transmission line. So the phase on extrapolation to DC is inherently zero, avoiding the need for constraint algorithms.
- The physical correspondence between the model and transmission line also provides greater insight when building mitigating algorithms. For example, seeing what poles exist on the transmission line is very helpful when building the DFE.

**Fitting a rational function to VNA data**

The first step is creating a model of the impairment using S4P data from the VNA. In this example, the S4P data includes about 1,500 frequencies from 50 MHz to 50 GHz. After reading the file into MATLAB via the RF Toolbox read function, we use the s2sdd function to extract the equivalent differential two-port behavior of this four-port network. The next step is to compute the transfer function and rational model. The frequency domain transfer function of the two-port parameters is calculated with the "s2tf" function. Then the "rationalfit" function is used to compute the time-domain modified rational function. The end result is that about 24,000 data points are condensed into a simple 48-pole rational function fit.

*1. Frequency response (above left) of a rational function model created from measured S-parameters. The model was used to create the eye diagram (above right) for analyzing intersymbol interference.*

**Modeling the backplane in Simulink**

The reformatting script works by setting the coefficients of several existing Simulink blocks, joining them into a simple structure, and collecting the result in a subsystem. The poles and residues of the rational function model are converted into numerator and denominator form for use in the Laplace Transform transfer function blocks. Each transfer function block represents either one real pole and residue or a pair of complex conjugate poles and residues. Either way, each transfer function block always has real coefficients.

In this example, the rational function model contains two real poles and residues and 10 pairs of complex poles and residues, so the model contains 12 transfer function blocks. The principle delay is modeled with a Transport Delay block. Then the subsystem is exercised by connecting a simple test harness consisting of a random message source connected to input. Scopes and a BER meter are used to quantify the impairment. Once the subsystem is performing as expected, the next stage, not covered in detail here, is to develop models of the mitigating algorithms, such as pre-emphasis filters and DFEs.

*2. The rational function model can be used in a Model-Based Design workflow, where algorithms that mitigate the impairment (such as preemphasis and equalization) are developed.*

**Modeling the Backplane in EDA tools**

We can use popular EDA tools to create the circuit-level design based on the algorithms we modeled. To verify the design we'd like to reuse the impairment model in the EDA environment. We can do this by exporting the modified rational function once more, this time as a behavioral Verilog-A module, a preferred form for EDA tools.

The module includes the Verilog-A "laplace_nd()" function with the appropriate numerator/denominator coefficients. The principle delay is created using the Verilog-A "absdelay()" function. We can then run this Verilog-A module inside an EDA tool to verify the design of the circuitry that implements the mitigating algorithms.

*3. The rational function model can be exported in Verilog-A behavioral format. This module is then imported into a mixed-signal circuit simulator, and is used in the design phase of Model-Based Design.*

**Design success**

This example shows how system architects are using RF techniques and Model-Based Design to rapidly develop signal integrity systems and algorithms. Model-Based Design involves the creation of executable models in a block diagram design environment using blocks that represent algorithms or subsystems. A key to the success of Model-Based Design is the existence of libraries of prebuilt standard data transmission algorithms or blocks, such as digital filters, transforms, and spectral analysis tools. Libraries of visual blocks enable BER plots, constellation diagrams, and eye diagrams to be quickly and easily added to models.

These libraries enable systems to be built extremely quickly by dragging and dropping the algorithms or blocks from a library into the model and then joining the blocks. This flexibility also enables models to be changed very easily and quickly. The result is that engineers can focus their efforts on what's important, namely the algorithms and systems being tested.

Model-Based Design offers several major advantages for signal integrity engineering. The biggest is that models can be changed much more easily and rapidly than C code. The behavior of blocks can be changed quickly by altering their parameters. Structural changes can be made promptly by adding or removing blocks from a model by dragging and dropping " without the need to recompile the model. The results of changes can be examined using the visual blocks, for example, to show the BER after code has been added to a model. This allows different designs and algorithms to be evaluated extremely quickly. C-coded models cannot offer this level of flexibility. This makes Model-Based Design especially appropriate to signal integrity engineering.

**About the Author**

Colin Warwick is an RF Product Manager at The MathWorks. He is focused on the verification of RF, analog, and mixed-signal subsystems in the context of Model-Based Design for signal processing and communications applications. Colin can be reached at colin.warwick@mathworks.com.

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